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m icroprocessor z ilog features z380 m icroprocessor n static cmos design with low-power standby mode option n 32-bit internal data paths and alu n operating frequency - dc-to-18 mhz at 5v - dc-to-10 mhz at 3.3v n enhanced instruction set that maintains object-code compatibility with z80 and z180 microprocessors n 16-bit (64k) or 32-bit (4g) linear address space n 16-bit data bus with dynamic sizing p roduct s pecification n two-clock cycle instruction execution minimum n four banks of on-chip register files n enhanced interrupt capabilities, including 16-bit vector n undefined opcode trap for z380 instruction set n on-chip i/o functions: - six-memory chip selects with programmable waits - programmable i/o waits - dram refresh controller n 100-pin qfp package general description the z380 microprocessor is an integrated high- performance microprocessor with fast and efficient through- put and increased memory addressing capabilities. the z380 offers a continuing growth path for present z80-or z180-based designs, while maintaining z80 cpu and z180 mpu object-code compatibility. the z380 mpu enhancements include an improved 280 cpu, expanded 4-gbyte space and flexible bus interface timing. an enhanced version of the z80 cpu is key to the z380 mpu. the basic addressing modes of the z80 micropro- cessor have been augmented as follows: stack pointer relative loads and stores, 16-bit and 24-bit indexed off- sets, and more flexible indirect register addressing, with all of the addressing modes allowing access to the entire 32-bit address space. additions made to the instruction set, include a full complement of 16-bit arithmetic and logical operations, 16-bit i/o operations, multiply and divide, plus a complete set of register-to-register loads and exchanges. the expanded basic register file of the z80 mpu micropro- cessor includes alternate register versions of the ix and iy registers. there are four sets of this basic z80 micropro- cessor register file present in the z380 mpu, along with the necessary resources to manage switching between the different register sets. all of the register-pairs and index registers in the basic z80 microprocessor register file are expanded to 32 bits.
m icroprocessor z ilog general description (continued) the z380 mpu expands the basic 64 kbyte z80 and z180 address space to a full 4 gbyte (32-bit) address space. this address space is linear and completely accessible to the user program. the i/o address space is similarly expanded to a full 4 gbyte (32-bit) range and 16-bit i/o, and both simple and block move are added. some features that have traditionally been handled by external peripheral devices have been incorporated in the design of the z380 microprocessor. the on-chip peripher- als reduce system chip count and reduce interconnection on the external bus. the z380 mpu contains a refresh controller for drams that employs a /cas-before-/ras refresh cycle at a programmable rate and burst size. six programmable memory-chip selects are available, along with programmable wait-state generators for each chip-select address range. the z380 mpu provides flexible bus interface timing, with separate control signals and timing for memory and i/o. the memory bus control signals provide timing refer- ences suitable for direct interface to dram, static ram, eprom, or rom. full control of the memory bus timing is possible because the /wait signal is sampled three times during a memory transaction, allowing complete user control of edge-to-edge timing between the reference signals provided by the z380 mpu. the i/o bus control signals allow direct interface to members of the z80 family of peripherals, the z8000 family of peripherals, or the z8500 series of peripherals. figure 1 shows the z380 block diagram; figure 2 shows the pin assignments. note: all signals with a preceding front slash, "/", are active low e.g., b//w (word is active low); b/w is active low, only) power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss external interface logic interrupts cpu refresh control clock with standby control chip selects and waits data (16) address (32) vdd vss /ev figure 1. z380 functional block diagram
m icroprocessor z ilog a23 a24 a25 a26 a27 a28 a29 a5 a4 a3 a2 a0 vss vdd vss vdd /trefr /trefa /trefc /bhen /blen /mrd /mwr a1 z380 100-pin qfp a30 a31 vss vdd vss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 vss 100 1 95 5 10 15 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 /msize /wait busclk ioclk /m1 /iorq /iord clki clko /iowr vss vdd vss d15 vdd 2 figure 2. 100-pin qfp pin assignments
m icroprocessor z ilog pin description a31-a0 address bus (outputs, active high, tri-state). these non-multiplexed address signals provide a linear memory address space of four gigabytes. the 32-address signals are also used to access i/o devices. /back bus acknowledge (output, active low, tri-state). this signal, when asserted, indicates that the z380 mpu has accepted an external bus request and has tri-stated its output drivers for the address bus, data bus and the bus control signals /trefr, /trefa, /trefc, /bhen, /blen, /mrd, /mwr, /iorq, /iord, and /iowr. note that the z380 mpu cannot provide any dram refresh transactions while it is in the bus acknowledge state. /bhen byte high enable (output, active low, tri-state). this signal is asserted at the beginning of a memory, or refresh transaction to indicate that an operation on d15-d8 is requested. for a 16-bit memory transaction, if /msize is asserted, indicating a byte-wide memory, another memory transaction is performed to transfer the data on d15-d8, this time through d15-d8. /blen byte low enable (output, active low, tri-state). this signal is asserted at the beginning of a memory or refresh transaction to indicate that an operation on d7-d0 is requested. for a 16-bit memory transaction, if /msize is asserted, indicating a byte-wide memory, only the data on d7-d0 will be transferred during this transaction, and another transaction will be performed to transfer the data on d15-d8, this time through d7-d0. /breq bus request (input, active low). when this signal is asserted, an external bus master is requesting control of the bus. /breq has higher priority than all nonmaskable and maskable interrupt requests. busclk bus clock (output, active high, tri-state). this signal, output by the z380 mpu, is the reference edge for the majority of other signals generated by the z380 mpu. busclk is a delayed version of the clk input. clki clock/crystal (input, active high). an externally generated direct clock can be input at this pin and the z380 mpu would operate at the clki frequency. alterna- tively, a crystal up to 20 mhz can be connected across clki and clko, and the z380 mpu would operate at half of the crystal frequency. the two clocking options are controlled by the clksel input. clko crystal (output, active high). crystal oscillator connection. this pin should be left open if an externally generated direct clock is input at the clki pin. clksel clock option select (input, active high). this input should be connected to v dd to select the direct clock option and should be connected to v ss for the crystal option. d15-d0 data bus (input/outputs, active high, tri-state). this bi-directional 16-bit data bus is used for data transfer between the z380 mpu and memory or i/o devices. note that for a memory word transfer, the even-addressed (a0 = 0) byte is generally transferred on d15-d8, and the odd-addressed (a0 = 1) byte on d7-d0 (see the /msize pin description). /ev evaluation mode (input, active low). this input should be left unconnected for normal operation. when it is driven to logic 0, the z380 mpu conditions itself in the reset mode and tri-states all of its output pin drivers. /halt halt status (output, active low, tri-state). if the z380 mpu standby mode option is not selected, a sleep instruc- tion is executed no different than a halt instruction, and the one halt signal goes active to indicate the cpu's halt state. if the standby mode option is selected, this signal goes active only at the halt instruction execution. /stnby standby status (output, active low, tri-state). if the z380 mpu standby mode is selected, executing a sleep instruction stops clocking within the z380 mpu and at busclk and ioclk after which this signal is asserted. the z380 mpu is then in the low power standby mode, with all operations suspended. /int3-0 interrupt requests (inputs, active low). these signals are four asynchronous maskable interrupt inputs. ioclk i/o clock (output, active high, tri-state). this signal is a program controlled divided-down version of busclk. the division factor can be two, four, six or eight with i/o transactions and interrupt-acknowledge transactions oc- curring relative to ioclk. /intak interrupt acknowledge status (output, active low, tri-state). this signal is used to distinguish between i/o and interrupt acknowledge transactions. this signal is high during i/o read and i/o write transactions and low during interrupt acknowledge transactions. /iorq input/output request (output, active low, tri-state). this signal is active during all i/o read and write transac- tions and interrupt acknowledge transactions.
m icroprocessor z ilog /reset reset (input, active low). this input must be active for a minimum of five busclk periods to initialize the z380 mpu. the effect of /reset is described in detail in the reset section. /trefa timing reference a (output, active low, tri-state). this timing reference signal goes low at the end of t2 and returns high at the end of t4 during a memory read, memory write or refresh transaction. it can be used to control the address multiplexer for a dram interface or as the /ras signal at higher processor clock rates. /trefc timing reference c (output, active low, tri-state). this timing reference signal goes low at the end of t3 and returns high at the end of t4 during a memory read, memory write or refresh transaction. it can be used as the /cas signal for dram accesses. /trefr timing reference r (output, active low, tri-state). this timing reference signal goes low at the end of t1 and returns high at the end of t4 during a memory read, memory write or refresh transaction. it can be used as the /ras signal for dram accesses. /umcs upper memory chip select (output, active low, tri- state). this signal is activated during a memory read, memory write, or optionally a refresh transaction when accessing the highest portion of the linear address space within the first 16 mbytes, but only if this chip select function is enabled. v dd power supply. these eight pins carry power to the device. they must be tied to the same voltage externally. v ss ground. these eight pins are the ground references for the device. they must be tied to the same voltage exter- nally. /wait wait (input, active low). this input is sampled by busclk or ioclk, as appropriate, to insert wait states into the current bus transaction. the conditioning and characteristics of the z380 mpu pins under various operation modes are defined in table 1. /m1 machine cycle one (output, active low, tri-state). this signal is active during interrupt acknowledge and reti transactions. /iord input, output read strobe (output, active low, tri- state). this signal is used strobe data from the peripherals during i/o read transactions. in addition, /iord is active during the special reti transaction and the i/o heartbeat cycle in the z80 protocol case. /iowr input/output write strobe (output, active low, tri- state). this signal is used to strobe data into the peripher- als during i/o write transactions. /lmcs low memory chip select ( output, active low, tri- state). this signal is activated during a memory read or memory write transaction when accessing the lower por- tion of the linear address space within the first 16 mbytes, but only if this chip select function is enabled. /mcs3-/mcs0 mid-range memory chip selects ( output, active low, tri-state). these signals are individually active during memory read or write transactions when accessing the mid-range portions of the linear address space within the first 16 mbytes. these signals can be individually enabled or disabled. /mrd memory read (output, active low, tri-state). this signal indicates that the addressed memory location should place its data on the data bus as specified by the /bhen and /blen control signals. /mrd is active from the end of t1 until the end of t4 during memory read transactions. /msize memory size (input, active low). this input, from the addressed memory location, indicates if it is word size (logic high) or byte size (logic low). in the latter case, the addressed memory should be connected to the d15-d8 portion of the data bus, and an additional memory transac- tion will automatically be generated to complete a word size data transfer. /mwr memory write (output, active low, tri-state). this signal indicates that the addressed memory location should store the data on the data bus, as specified by the /bhen and /blen control signals. /mwr is active from the end of t2 until the end of t4 during memory write transactions. /nmi nonmaskable interrupt (input, falling edge-triggered). this input has higher priority than the maskable interrupt inputs /int3-int0.
m icroprocessor z ilog pin description (continued) table 1. z380 mpu pin conditioning characteristics operation mode conditions normal bus relinquish pin /breq=1,/back=1, /breq=0,/back=0, names /ev=nc /ev=nc evaluation clki input input input clko output/no connection output/no connection no connection clksel input input input busclk output output tri-state ioclk output output tri-state a31-a0 output tri-state tri-state d15-d0 input/output tri-state tri-state /trefr,/trefa, output tri-state tri-state /trefc /mrd,/mwr output tri-state tri-state /bhen,/blen output tri-state tri-state /lmcs,/umcs, output tri-state tri-state /mcs3-mcs0 /msize,/wait input input input /halt,/stnby output output tri-state /m1,/intak output output tri-state /iorq,/iord, output tri-state tri-state /iowr /breq input input input /back output output tri-state /nmi,/int3-/int0 input input input /reset input input input /ev no connection no connection input v dd power power power v ss ground ground ground
m icroprocessor z ilog external interface two kinds of operations can occur on the system bus: transactions and requests. at any given time, one device (either the cpu or a bus master) has control of the bus and is known as the bus master. this section shows all of the transaction and request timing for the device. for the sake of clarity, there are more figures than are actually necessary. this should aid the reader rather than confuse. in all of the timing diagram figures, the row labelled status encompasses /bhen, /blen, and the chip select signals. transactions a transaction is initiated by the bus master and is re- sponded to by some other device on the bus. only one transaction can proceed at a time; six kinds of transactions can occur: memory, refresh, i/o, interrupt acknowledge, reti (return from interrupt), and halt. the z380 mpu is unique in that memory and i/o bus transactions use separate control signals. this allows the memory interface to be optimized independently of the i/o interface. memory transactions memory transactions move instructions or data to or from memory when the z380 mpu performs a memory access. thus, they are generated during program execution to fetch instructions from memory and to fetch and store memory data. they are also generated to store old pro- gram status and fetch new program status during interrupt and trap handling, and are used by dma peripherals to transfer information. a memory transaction is two clock cycles long unless extended with wait states. wait states may be inserted between each of the four t states in a memory transaction and are one busclk cycle long per wait state. the external /wait input is sampled only after any internally-generated wait states are inserted. memory transactions may transfer either bytes or words. if the z380 mpu attempts to transfer a word to a byte-wide memory, the /msize signal should be asserted low to force this transaction to be byte-wide dynamically. the z380 mpu will then perform another memory transaction to transfer the byte that was not transferred during the first transac- tion. read memory transactions are shown without wait states, with wait states between t1 and t2, between t2 and t3, and between t3 and t4 (figures 3a-d). the data bus is driven by the memory being addressed, and the memory data is latched immediately before the rising edge of busclk which terminates t4.
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t4 figure 3a. read cycle, no waits
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t1l t1h t2 t3 t4 figure 3b. read cycle, t1 wait
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t2h t2l t3 t4 external interface (continued) figure 3c. read cycle, t2 wait
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t3l t3h t4 figure 3d. read cycle, t3 wait
m icroprocessor z ilog external interface (continued) write memory transactions are shown without wait states, with wait states between t1 and t2, between t2 and t3, and between t3 and t4 (figures 4a-d). the /mwr strobe is activated at the end of t1, to allow write data setup time for the memory since the write data is driven on to the data bus at the beginning of t1. busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t4 figure 4a. write cycle, no waits
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t1l t1h t2 t3 t4 figure 4b. write cycle, t1 wait
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t2h t2l t3 t4 figure 4c. write cycle, t2 wait
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t3l t3h t4 figure 4d. write cycle, t3 wait
m icroprocessor z ilog external interface (continued) refresh transactions a memory refresh transaction is generated by the z380 mpu refresh controller and can occur immediately after the final clock cycle of any other transaction. the address during the refresh transaction is not defined as the cas-before-ras refresh cycle is assumed, which uses the on-chip refresh address generator present on drams. prior to the first refresh transaction, a refresh setup cycle is performed to guarantee that the /cas precharge time is met. this refresh setup cycle is present only prior to the first busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr tph tpl refresh transaction in a burst (figure 5). refresh transac- tions are shown without wait states, with wait states be- tween t1 and t2, between t2 and t3, and between t3 and t4 (figures 6a-d). note that during the refresh cycle the data bus is continuously driven, /mrd and /mwr remain inactive, /bhen and /blen are active to enable all /cas signals to the drams, and those chip select signals enabled for dram refresh transactions are active. figure 5. refresh setup
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t4 figure 6a. refresh cycle, no waits
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t1l t1h t2 t3 t4 figure 6b. refresh cycle, t1 wait
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t2h t2l t3 t4 figure 6c. refresh cycle, t2 wait
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t1 t2 t3 t3l t3h t4 figure 6d. refresh cycle, t3 wait
m icroprocessor z ilog i/o transactions i/o transactions move data to or from an external periph- eral when the z380 mpu performs an i/o access. all i/o transactions occur referenced to the ioclk signal, when it is a divided-down version of the busclk signal. busclk may be divided by a factor of from two to eight to form the ioclk, under program control. an example of this division is shown, for the four possible divisors, in figure 7. note that the ioclk divider is synchronized (i.e., starts with a known timing relationship) at the trailing edge of /reset. this is discussed in the reset section. busclk ioclk (x2) ioclk (x4) ioclk (x6) ioclk (x8) figure 7. ioclk timing
m icroprocessor z ilog external interface (continued) the z380 mpu is unique in that it employs separate control signals for accessing the memory and i/o. this allows the two interfaces to be optimized independent of one an- other. the i/o bus control signals allow direct connection to members of the z80 family of peripherals of the z8500 family of peripherals. note that because all i/o bus transactions start on a rising edge of ioclk, there may be up to n busclk cycles of latency between the execution unit request for the transac- tion and the transaction actually starting, where n is the programmed clock divisor for ioclk. this implies that the lowest possible divisor should always be used for ioclk. all i/o transactions are four ioclk cycles long unless extended by wait states. wait states may be inserted between the third and fourth ioclk cycles in an i/o transaction and are one ioclk cycle per wait state. the external /wait input is sampled only after internally-gener- ated wait states are inserted. i/o read transactions are shown with and without a wait state (figures 8a-b). the contents of the data bus is latched immediately before the falling edge of ioclk during the last ioclk cycle of the transaction. ioclk address data /wait /mi /iorq /iord /intak /iowr figure 8a. i/o read cycle, no waits
m icroprocessor z ilog ioclk address data /wait /mi /iorq /iowr /intak /iord figure 8b. i/o read cycle, t1 wait
m icroprocessor z ilog external interface (continued) i/o write transactions are shown with and without a wait state (figures 9a-b). the data bus is driven throughout the transaction. ioclk address data /wait /iorq /iord /iowr /intak /mi figure 9a. i/o write cycle, no waits
m icroprocessor z ilog ioclk address data /wait /mi /iorq /iord /iowr /intak figure 9b. i/o write cycle, t1 wait
m icroprocessor z ilog external interface (continued) interrupt acknowledge transactions an interrupt acknowledge transaction is generated by the z380 mpu in response to an unmasked external interrupt request. figure 10a shows an interrupt acknowledge transaction in response to /int0 and figure 10b shows an interrupt acknowledge transaction in response to either one of /int-3. note that because all i/o bus transactions start on a rising edge of ioclk, there may be up to n busclk cycles of latency between the execution unit request for the transaction and the transaction actually starting (where n is the programmed clock divisor for ioclk). ioclk address data /wait /m1 /iorq /iord /iowr /intak figure 10a. interrupt acknowledge cycle, /int0
m icroprocessor z ilog ioclk address data /wait /mi /intak /iord /iowr /iorq an interrupt acknowledge transaction for /int0 is five ioclk cycles long unless extended by wait states. /wait is sampled at two separate points during the transaction. /wait is first sampled at the end of the first ioclk cycle during the transaction. wait states inserted here allow the external daisy-chain between peripherals with a longer time to settle before the interrupt vector is requested. /wait is then sampled at the end of the fourth ioclk cycle to delay the point at which the interrupt vector is read by the z380 mpu, after it has been requested. the interrupt vector may be either eight or sixteen bits, under program control, and is latched by the falling edge of ioclk in the last cycle of the interrupt acknowledge transaction. when using mode 0 interrupts, where the z380 mpu fetches an instruction from the interrupting device, these fetches are always eight bits wide and are transferred over d7-d0. an interrupt acknowledge transaction in response to one of /int3-/int1 is also five ioclk cycles long, unless extended by wait states. the waits are sampled and inserted at similar locations as an interrupt acknowledge transaction is for /int0. note, however, only the /intak signal is active with /mi, /iorq, /iord and /iowr held inactive. for either type of intack transaction the address bus is driven with a value which indicates the type of interrupt being acknowledged as follows: a31-a6 are all one, and a3-a0 are one except for a single zero corresponding to the maskable interrupt being acknowledged. thus an /int3 acknowledge is signaled by a3 being zero during the interrupt acknowledge transaction, /int2 acknowl- edge is signalled by a2 being zero, etc. reti transactions the reti transaction is generated whenever an reti instruction is executed by the z380 mpu. this transaction is necessary because z80 family peripherals are de- signed to watch instruction fetches and take special action upon seeing a reti instruction (this is the only instruction that the z80 family peripherals watch for). since the z380 mpu fetches instructions using the memory control sig- nals, a simulated reti instruction fetch must be placed on the bus with the appropriate i/o bus control signals. this is shown in figure 11. again, note that because all i/o bus transactions start on a rising edge of ioclk, there may be up to n busclk cycles of latency between the execution unit request for the transaction and the transaction actually starting, where n is the programmed clock divisor for ioclk. figure 10b. interrupt acknowledge cycle, /int3-1
m icroprocessor z ilog external interface (continued) ioclk address data /wait /m1 /iorq /iord /iowr eded 4d4d 1 2 3 4 5 6 7 8 9 10 /intak figure 11. return from interrupt cycle the reti transaction is ten ioclk cycles long unless extended by wait states, and /wait is sampled at three separate points during the transaction. /wait is first sampled in the middle of the third ioclk cycle to allow for longer /iord low-time requirements. /wait is then sampled again during the middle of the fifth ioclk cycle to allow for longer internal daisy-chain settling time within the periph- eral. wait states inserted here have the effect of separating what the peripheral sees as two separate instruction fetch cycles. finally, /wait is sampled in the middle of the ninth ioclk cycle, again to allow for longer /iord low-time requirements. the z380 mpu drives the data bus throughout the reti transaction, with ededh during the first half of the transac- tion (the first byte of a reti instruction is edh) and with 4d4dh during the second half of the transaction (the second byte of an reti instruction is 4dh). halt transactions a halt transaction occurs whenever the z380 mpu ex- ecutes a halt instruction, with the /halt signal activated on the falling edge of busclk. if the standby mode is not enabled, executing a sleep instruction would also cause a halt transaction to occur. while in the halt state, the z380 mpu continues to drive the address and data buses, and the /halt signal remains active until either an interrupt request is acknowledged or a reset is received. refresh transactions may occur while in the halt state and the bus can be granted. the timing of entry into the halt state is shown in figure 12, while the timing of exiting from halt state is shown in figure 13.
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t5 thl thh thl /halt figure 12. halt entry
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr thh thl thh thl thh t6 /halt /int or /nmi figure 13. halt exit
m icroprocessor z ilog requests a request can be initiated by a device that does not have control of the bus. two types of request can occur: bus request and interrupt request. when an interrupt or bus request is made, it is answered by the cpu according to its type. for an interrupt request, the cpu initiates an interrupt acknowledge transaction and for bus requests, the cpu enters the bus disconnect state, relinquishes the bus, and activates an acknowledge signal. bus requests to generate transactions on the bus, a potential bus master (such as a dma controller) must gain control of the bus by making a bus request. a bus request is initiated by driving /breq low. several bus requesters may be wired- or to the /breq pin; priorities are resolved externally to the cpu, usually by a priority daisy chain. the asynchronous /breq signal generates an internal /busreq, which is synchronous. if the /breq is active at the beginning of any transaction, the internal /busreq causes the /back signal to be asserted after the current transaction is completed. the z380 mpu then enters the bus disconnect state and gives up control of the bus. all z380 mpu control signals, except /back, /mi and /intak are tri-stated. note that release of the bus may be inhibited under program control to allow the z380 mpu exclusive access to a shared resource; this is controlled by the setc lck and resc lck instructions. entry into the bus dis- connect state is shown in figure 14. the z380 mpu regains control of the bus after /breq is deasserted. this is shown in figure 15. interrupt requests the z380 mpu supports two types of interrupt requests, maskable /int3-int0 and nonmaskable (/nmi). the inter- rupt request line of a device that is capable of generating an interrupt can be tied to either /nmi or one of the maskable interrupt request lines, and several devices can be connected to one interrupt request line with the devices arranged in a priority daisy chain. however, because of the need for z80 family peripheral devices to see the reti instruction, only one daisy chain of z80-family peripherals can be used. the z380 mpu handles maskable and nonmaskable interrupt requests somewhat differently, as follows: any high-to-low transition on the /nmi input is asynchro- nously edge-detected, and the internal nmi latch is set. at the beginning of the last clock cycle in the last internal machine cycle of any instruction, the maskable interrupts are sampled along with the state of the nmi latch. if an enabled maskable interrupt is requested, at the next possible time (the next rising edge of ioclk) an interrupt acknowledge transaction is generated to fetch the inter- rupt vector from the interrupting device. for a nonmaskable interrupt, no interrupt acknowledge transaction is gener- ated; the nmi service routine always starts at address 00000066h.
m icroprocessor z ilog external interface (continued) busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t7 tbl /breq /back transaction in progress /mi /iorq /iord /iowr /intak figure 14. bus request/acknowledge cycle
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr tbh til /breq /back /mi /iorq /iord /iowr tbh tbl tbh tbl /intak figure 15. bus request/acknowledge end cycle
m icroprocessor z ilog idle cycles when no transactions are being performed on the bus, an idle cycle occurs (figure 16). all control signals, for both memory and i/o, are inactive during the idle cycle. busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr tih til external interface (continued) miscellaneous timing there are two cases where a specific transaction is not taking place on the bus which are illustrated in this section: the bus idle cycle and the i/o heartbeat cycle. figure 16. idle cycle
m icroprocessor z ilog i/o heartbeat cycle the z380 mpu is capable of generating an i/o heartbeat cycle on the i/o bus in response to an i/o write to an on- chip control register. this cycle is most useful with z80 family peripherals, where some members require a trans- action that looks like a z80 cpu instruction fetch to perform certain interrupt functions (figure 17). ioclk address data /wait /mi /iorq /iord /iowr all zeros / intak figure 17. i/o heartbeat cycle
m icroprocessor z ilog external interface (continued) reset timing the timing for entering and exiting the reset state is shown in figures 18 and 19. the effects of reset on the internal state of the z380 mpu are detailed in the reset section. the synchronization of ioclk at the end of the reset state is shown in figure 20. note that the ioclk divisor is set to the maximum value (eight) by /reset and is only synchro- nized at the end of the reset state. busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr t9 trl /ioctl3-0 /reset transaction in progress figure 18. reset entry
m icroprocessor z ilog busclk address data status /wait /msize /trefr /trefa /trefc /mrd /mwr trh til /ioctl3-0 /reset trh trl trh trl figure 19. reset exit
m icroprocessor z ilog external interface (continued) busclk /reset ioclk figure 20. ioclk reset start-up
m icroprocessor z ilog cpu architecture the central processing unit (cpu) of the z380 mpu is a binary-compatible extension of the z80 cpu and z180 cpu architectures. high throughput rates for the z380 cpu are achieved by a high clock rate, high bus band- width and instruction fetch/execute overlap. communicat- ing to the external world through an 8- or 16-bit data bus, the z380 cpu is a full 32-bit machine internally, with a 32-bit alu and 32-bit registers. modes of operation the z380 cpu can operate in either native or extended mode, as controlled by a bit in the select register (sr). in native mode (the reset configuration), all address manipulations are performed modulo 65536 (16 bits). in this mode the program counter (pc) only increments across 16 bits, all address manipulation instructions (in- crement, decrement, add, subtract, indexed, stack rela- tive, and pc relative) only operate on 16 bits, and the stack pointer (sp) only increments and decrements across 16 bits. the program counter high-order word is left at all zeros, as is the high-order words of the stack pointer and the i register. thus native mode is fully compatible with the z80 cpu's 64 kbyte address space. it is still possible to address memory outside of the 64 kbyte address space for data storage and retrieved in native mode, however, direct addresses, indirect addresses, and the high-order word of the sp, i and the ix and iy registers may be loaded with non-zero values. but executed code and interrupt service routines must reside in the lowest 64 kbytes of the address space. in extended mode, however, all address manipulation instructions operate on 32 bits, allowing access to the entire 4 gbyte address space of the z380 mpu. in both native and extended modes, the z380 cpu drives all 32 bits of the address onto the external address bus; only the width of manipulated addresses distinguish native from extended mode. the z380 cpu implements one instruc- tion to allow switching from native to extended mode, but once in extended mode, only reset returns the z380 mpu to native mode. this restriction applies because of the possibility of "misplacing" interrupt service routines or vector tables during the translation from extended mode back to native mode. in addition to native and extended mode, which is specific to memory space addressing, the z380 mpu can operate in either word or long word mode specific to data load and exchange operations. in word mode (the reset con- figuration), all word load and exchange operations ma- nipulate 16-bit quantities. for example, only the low-order words of the source and destination are exchanged in an exchange operation, with the high-order words unaffected. in long word mode, all 32 bits of the source and destina- tion are directives to allow switching between word and long word mode; setc lw (set control long word) and resc lw (reset control long word) perform a global switch, while ddir w, ddir lw and their variants are decoder directives that select a particular mode only for the instruction that they precede. note that all word data arithmetic (as opposed to address manipulation arithmetic), rotate, shift and logical opera- tions are always in 16-bit quantities. they are not con- trolled by either the native/extended or word/long word selections. the exceptions to the 16-bit quantities are, of course, those multiply and divide operations with 32-bit products or dividends. lastly, all word input/output operations are performed on 16-bit values.
m icroprocessor z ilog cpu architecture (continued) address spaces the z380 cpu architecture supports five distinct address spaces corresponding to the different types of locations that can be accessed by the cpu. these five address spaces are: cpu register space, cpu control register space, memory address space, and i/o address space (on-chip and external). cpu register space the cpu register space is shown in figure 21 and consists of all of the registers in the cpu register file. these cpu registers are used for data and address manipulation, and are an extension of the z80 cpu register set, with four sets of this extended z80 cpu register set present in the z380 cpu. access to these registers is specified in the instruc- tion, with the active register set selected by bits in the select register (sr) in the cpu control register space. each register set includes the primary registers a, f, b, c, d, e, h, l, ix, and iy, as well as the alternate registers a, f, b, c, d, e, h, l, ix, and iy. these byte registers can be paired b with c, d with e, h with l, b with c, d with e and h with l to form word registers. these word registers are extended to 32 bits with the z extension to the register. this register extension is only accessible when using the register as a 32-bit register (the long word mode) or when swapping between the most-significant and least-signifi- cant word of a 32-bit register. whenever an instruction refers to a word register, the implicit size is controlled by the word or long word mode. also included are the r, i and sp registers, as well as the pc. a f b c d e h l ixu ixl iyu iyl a' f' b' c' d' e' h' l' ixu' ixl' iyu' iyl' bcz' dez' hlz' ixz' iyz' bcz dez hlz ixz iyz r i spz pcz iz sp pc 4 sets of registers figure 21. register set
m icroprocessor z ilog cpu control register space the cpu control register space consists of the 32-bit select register (sr), figure 22. the sr may be accessed as a whole or the upper three bytes of the sr may be accessed individually as the ysr, xsr, and dsr. in addition, these upper three bytes can be loaded with the same byte value. the sr may also be pushed and poped and is cleared to all zeros on reset. reserved (0) 23 2122 17 iybank iyp reserved (0) ixbank ixp 20 1819 16 31 2930 25 28 2627 24 xsr ysr reserved (0) 7 56 1 mainbank alt xm im afp 4 23 0 15 1314 9 12 1011 8 dsr lw ief1 0 lck figure 22. select register iybank (iy bank select). this 2-bit field selects the register set to be used for the iy and iy' registers. this field can be set independently of the register set selection for the other z380 cpu registers. reset selects bank 0 for iy and iy'. iyp (iy prime register select). this bit controls and reports whether iy or iy' is the currently active register. iy is selected when this bit is cleared and iy' is selected when this bit is set. reset clears this bit and selects iy. ixbank (ix bank select). this 2-bit field selects the register set to be used for the ix and ix' registers. this field can be set independently of the register set selection for the other z380 cpu registers. reset selects bank 0 for ix and ix'. ixp (ix prime register select). this bit controls and reports whether ix or ix' is the currently active register. ix is selected when this bit is cleared and ix' is selected when this bit is set. reset clears this bit and selects ix. mainbank (main bank select). this 2-bit field selects the register set to be used for the a, f, bc, de, hl, a', f', bc', de' and hl' registers. this field can be set independently of the register set selection for the other z380 cpu regis- ters. reset selects bank 0 for these registers. alt (bc/de/hl or bc'/de'/hl' register select). this bit controls and reports whether bc/de/hl or bc'/de'/hl' is the currently active bank of registers. bc/de/hl are selected when this bit is cleared and bc'/de'/hl' are selected when this bit is set. reset clears this bit, selecting bc/de/hl.
m icroprocessor z ilog cpu architecture (continued) xm (extended mode). this bit controls the extended/ native mode selection for the z380 cpu. this bit is set by the setc xm instruction, and once set, it can be cleared only by a reset on the /reset pin. when this bit is set, the z380 cpu is in extended mode. reset clears this bit and the z380 cpu is in native mode. lw (long word mode). this bit controls the long word/ word mode selection for the z380 cpu. this bit is set by the setc lw instruction and cleared by the resc lw instruction. when this bit is set, the z380 cpu is in long word mode; when this bit is cleared, the z380 cpu is in word mode. reset clears this bit. note that individual instructions may be executed in either word or long word load and exchange mode, using the ddir w and ddir lw decoder directives. ief1 (interrupt enable flag). this bit is the master interrupt enable for the z380 cpu. this bit is set by the ei instruction and cleared by the di instruction. when this bit is set, interrupts are enabled; when this bit is cleared, interrupts are disabled. reset clears this bit. im (interrupt mode). this 2-bit field controls the interrupt mode for the /int0 interrupt request. these bits are controlled by the im instructions (00 = im 0, 01 = im 1, 10 = im 2, 11 = im 3). reset clears both of these bits, selecting interrupt mode 0. lck (lock). this bit controls the lock/ unlock status of the z380 cpu. this bit is set by the setc lck instruction and cleared by the resc lck instruction. when this bit is set, no bus requests are accepted, providing exclusive ac- cess to the bus by the z380 cpu. when this bit is cleared the z380 cpu will grant bus requests in the normal fashion. reset clears this bit. afp (af prime register select). this bit controls and reports whether af or af' is the currently active pair of registers. af is selected when this bit is cleared and af' is selected when this bit is set. reset clears this bit and selects af.
m icroprocessor z ilog memory address space the memory address space can be viewed as a string of 4 gbyte numbered consecutively in ascending order. the 8-bit byte is the basic addressable element in the z380 mpu memory address space. however, there are other addressable data elements; bits, 2-byte words, byte strings, and 4-byte words. the size of the data element being addressed depends on the instruction being executed as well as the word/long word mode. a bit can be addressed by specifying a byte, and a bit within that byte. bits are numbered from right to left, with the least significant bit being bit 0 (figure 23). the address of a multiple-byte entity is the same as the address of the byte with the lowest memory address in the entity. multiple-byte entities can be stored beginning with either even or odd memory addresses. a word (either 2-byte or 4-byte entity) is aligned if its address is even; otherwise, it is unaligned. multiple bus transactions, which may be required to access multiple-byte entities, can be minimized if alignment is maintained. the formats of multiple-byte data types are also shown in figure 23. note that when a word is stored in memory, the least significant byte precedes the more significant byte of the word, as in the z80 cpu architecture. also, the lower- addressed byte is present on the upper byte of the external data bus. 7 6 5 4 3 2 1 0 bits within a byte: 16-bit word at address n: least significant byte most significant byte address n address n+1 32-bit word at address n: d7-0 (least significant byte) d15-8 address n address n+1 address n+2 address n+3 d31-24 (most significant byte) d23-16 memory addresses: least significant byte even address (a0=0) most significant byte odd address (a0=1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 23. bit/byte ordering conventions
m icroprocessor z ilog cpu architecture (continued) external i/o address space external i/o addresses are generated by i/o instructions, except those reserved for on-chip i/o address space accesses, and can take a variety of forms (table 2). an i/o read or write is always one transaction, regardless of the bus size and the type of i/o instruction. on-chip i/o address space the z380 mpu's on-chip peripheral functions and a por- tion of its interrupt functions are controlled by several on-chip registers, which occupy an on-chip i/o address space. this on-chip i/o address space can be accessed only with the following reserved on-chip i/o instructions. table 2. external i/o addressing options address bus i/o instruction a31-a24 a23-a16 a15-a8 a7-a0 in a, (n) 00000000 00000000 contents of a reg n in dst,(c) bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 in0 dst,(n) 00000000 00000000 00000000 n ina(w) dst,(mn) 00000000 00000000 m n ddir ib ina(w) dst,(lmn) 00000000 l m n ddir iw ina(w) dst,(klmn) k l m n block input bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 out (n),a 00000000 00000000 contents of a reg n out (c),dst bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 out0 (n),dst 00000000 00000000 00000000 n outa(w) (mn),dst 00000000 00000000 m n ddir ib outa(w) (lmn),dst 00000000 l m n ddir iw outa(w) (klmn),dst k l m n block output bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 in0 r, (n) otim in0 (n) otimr out0 (n), r otdm tstio n otdmr when one of these i/o instructions is executed, the z380 mpu outputs the register address being accessed in a pseudo transaction of two busclk cycles duration, with the address signals a31-a8 all at zeros. in the pseudo transaction, all bus control signals are at their inactive states.
m icroprocessor z ilog data types the z380 cpu can operate on bits, binary-coded decimal (bcd) digits (4 bits), bytes (8 bits), words (16 bits or 32 bits), byte strings, and word strings. bits in registers can be set, cleared, and tested. bcd digits, packed two to a byte, can be manipulated with the decimal adjust accu- mulator instruction (in conjunction with binary addition and subtraction) and the rotate digit instructions. bytes are operated on by 8-bit load, arithmetic, logical, and shift and rotate instructions. words are operated on in a similar manner by the word load, arithmetic, logical, and shift and rotate instructions. block move and search operations can manipulate byte strings and word strings up to 64 kbytes or words long. block i/o instructions have identical capa- bilities. cpu registers the z380 cpu contains abundant register resources (fig- ure 21). at any given time, the program has immediate access to both the primary and alternate registers in the selected register set. changing register sets is a simple matter of a ldctl instruction. primary and working registers the working register set is divided into the two register files; the primary file and the alternate (designated by ) file. each file contains an 8-bit accumulator (a), a flag register (f), and six general-purpose registers (b, c, d, e, h, and l). only one file can be active at any given time, although data in the inactive file can still be accessed. upon reset, the primary register file in register set 0 is active. exchange instructions allow the programmer to exchange the active file with the inactive file. the accumulator is the destination register for 8-bit arith- metic and logical operations. the six general-purpose registers can be paired (bc, de, and hl), and are extended to 32 bits by the z extension to the register, to form three 32-bit general-purpose registers. the hl regis- ter serves as the 16-bit or 32-bit accumulator for word operations. cpu flag register the flag register contains six flags that are set or reset by various cpu operations. this register is illustrated in fig- ure 24 and the various flags are described below. carry (c). this flag is set when an add instruction gener- ates a carry or a subtract instruction generates a borrow. certain logical, rotate and shift instructions affect the carry flag. add/subtract (n). this flag is used by the decimal adjust accumulator instruction to distinguish between add and subtract operations. the flag is set for subtract operations and cleared for add operations. parity/overflow (p/v). during arithmetic operations this flag is set to indicate a twos complement overflow. during logical and rotate operations, this flag is set to indicate even parity of the result or cleared to indicate odd parity. half carry (h). this flag is set if an 8-bit arithmetic operation generates a carry or borrow between bits 3 and 4, or if a 16-bit operation generates a carry or borrow between bits 11 and 12, or if a 32-bit operation generates a carry or borrow between bits 27 and 28. this bit is used to correct the result of a packed bcd addition or subtract operation. zero (z). this flag is set if the result of an arithmetic or logical operation is a zero. sign (s). this flag stores the state of the most significant bit of the accumulator. index registers the four index registers, ix, ix, iy and iy, each hold a 32-bit base address that is used in the indexed addressing mode. the index registers can also function as general- purpose registers with the upper and lower byte of the lower 16 bits being accessed individually. these byte registers are called ixu, ixu, ixl and ixl for the ix and ix registers, and iyu, iyu, iyl and iyl for the iy and iy registers. interrupt register the interrupt register (i) is used in interrupt modes 2 and 3 for /int0 to generate a 32-bit indirect address to an interrupt service routine. the i register supplies the upper twenty-four or sixteen bits of the indirect address and the interrupting peripheral supplies the lower eight or sixteen bits. in the assigned vectors mode for /int1-3 the upper sixteen bits of the vector are supplied by the i register; bits 15-9 are the assigned vector base and bits 8-0 are the assigned vector unique to each of /int1-3. s z x h x p/v n c 7 6 5 4 3 2 1 0 figure 24. cpu flag register
m icroprocessor z ilog data types program counter the program counter (pc) is used to sequence through instructions in the currently executing program and to generate relative addresses. the pc contains the 32-bit address of the current instruction being fetched from memory. in the native mode, the pc is effectively only 16 bits long, as carries from bit 15 to bit 16 are inhibited in this mode. in extended mode, the pc is allowed to increment across all 32 bits. r register the r register can be used as a general-purpose 8-bit read/write register. the r register is not associated with the refresh controller and its contents are changed only by the user. stack pointer the stack pointer (sp) is used for saving information when an interrupt or trap occurs and for supporting subroutine calls and returns. stack pointer relative addressing allows parameter passing using the sp. select register the select register (sr) controls the register set selection and the operating modes of the z380 cpu. the reserved bits in the sr are for future expansion; they will always read as zeros and should be written with zeros for future compatibility. the sr is shown in figure 22. addressing modes addressing modes are used by the z380 cpu to calculate the effective address of an operand needed for execution of an instruction. seven addressing modes are supported by the z380 cpu. of these seven, one is an addition to the z80 cpu addressing modes (stack pointer relative) and the remaining six modes are either existing or extensions to the z80 cpu addressing modes. register. the operand is one of the 8-bit registers (a, b, c, d, e, h, l, ixu, ixl, iyu, iyl, a', b', c', d', e', h' or l'); or is one of the 16-bit or 32-bit registers (bc, de, hl, ix, iy, bc', de', hl', ix', iy' or sp) or one of the special registers (i or r). immediate. the operand is in the instruction itself and has no effective address. the ddir ib and ddir iw decoder directives allow specification of 24-bit and 32-bit immedi- ate operands, respectively. indirect register. the contents of a register specify the effective address of an operand. the hl register is the primary register used for memory accesses, but bc and de can also be used. (for the jp instruction, ix and iy can also be used for indirection.) the bc register is used for i/o space accesses. direct address. the effective address of the operand is the location whose address is contained in the instruc- tion. depending on the instruction, the operand is either in the i/o or memory address space. sixteen bits of direct address is the norm, but the ddir ib and ddir iw decoder directives allow 24-bit and 32-bit direct addresses, respectively. indexed. the effective address of the operand is the location computed by adding the two's-complement signed displacement contained in the instruction to the contents of the ix or iy register. eight bits of index is the norm, but the ddir ib and ddir iw decoder directives allow 16-bit and 24-bit indexes, respectively. program counter relative. an 8-, 16- or 24-bit displace- ment contained in the instruction is added to the program counter to generate the effective address. this mode is available only for jump and call instructions. stack pointer relative. the effective address of the operand is the location computed by adding the two's- complement signed displacement contained in the in- struction to the contents of the stack pointer. eight bits of index is the norm, but the ddir ib and ddir iw decoder directives allow 16- and 24-bit indexes, respectively.
m icroprocessor z ilog instruction set the z380 cpus instruction set is a superset of the z80 cpus; the z380 cpu is opcode compatible with the z80 cpu. thus a z80 program can be executed on a z380 mpu without modification. the instruction set is divided into seventeen groups by function: the instructions are divided into the following categories. n 8-bit load group n 16/32 bit load group n push/pop group n exchanges, block transfers, and searches n 8-bit arithmetic and logic operations n general purpose arithmetic and cpu control n decoder directive instructions n 16/32 bit arithmetic operations n multiply/divide instruction group n 8-bit rotates and shifts n 16-bit rotates and shifts n 8-bit bit set, reset, and test operations n jumps n calls, returns, and restarts n 8-bit input and output operations for external i/o address space n 8-bit input and output operations for internal i/o address space n 16-bit input and output operations instruction set the following is a summary of the z380 instruction set which shows the assembly language mnemonic, the op- eration, the flag status, and gives comments on each instructions. note that mnemonic and object code assignment for newly added instructions (instructions in italic face) are prelimi- nary and subject to change without notice. the z380 technical manual will contain significantly more details for programming use. a list of instructions, as well as encoding is included in appendix a of this document. instruction set notation symbols. the following symbols are used to describe the instruction set. n an 8-bit constant nn a 16-bit constant d an 8-bit offset. (2s complement) r any one of the cpu register a, b, c, d, e, h, l s any 8-bit location for all the addressing modes allowed for the particular in- struction. dd,qq,ss,tt,uu any 16-bit location for all the address- ing modes allowed for the particular instruction. xxh ms byte of the specified 16-bit location xxl ls byte of the specified 16-bit location sr select register xy index register (ix or iy) xyz index register extend (ixz or iyz) xyu ms byte of index register (ixu or iyu) xyl ls byte of index register (ixl or iyl) sp current stack pointer (c) i/o port pointed by c register cc condition code [ ] optional field ( ) indirect address pointer or direct address
m icroprocessor z ilog instruction set (continued) assignment of a value is indicated by the symbol ? . for example, dst ? dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. the notation dst (b) is used to refer bit b of a given location, dst(m-n) is used to refer bit location m to n of the destina- tion. for example, hl(7) specifies bit 7 of the destination. and hl(23-16) specifies bit location 23 to 16 of the hl register. flags. the f register contains the following flags followed by symbols. s sign flag z zero flag h half carry flag p/v parity/overflow flag n add/subtract flag c carry flag the flag is affected according to the result of the operation. the flag is unchanged by the operation. 0 the flag is reset to 0 by operation. 1 the flag is set to 1 by operation. v p/v flag affected according to the overflow result of the operation. p p/v flag affected according to the parity result of the operation. condition codes. the following symbols describe the condition codes. z zero* nz not zero* c carry* nc no carry* s sign ns no sign nv no overflow v overflow pe parity even po parity odd p positive m minus *abbreviated set field encoding the convention for opcode binary format is shown in the following tables. for example, to get the opcode format on the instruction ld (ix+12h), c; first find out the entry for ld (xy+d),r. that entry has an opcode format of: 11 y11 101 01 110 r ?? d ?? at the bottom of each table (between table and notes), the binary format is the following: r , r r e g s r e g s y x y 000 b 000 b 0 ix 001 c 001 c 1 iy 010 d 010 d 011 e 011 e 100 h 100 ixu (x = 0),iyu(x = 1) 101 l 101 ixl (x = 0),iyl(x = 1) 111 a 111 a to form the opcode first look for the y field value for the ix register, which is 0. then find r field value for the c register, which is 001. replace the y and r fields with the value from the table; replace d value with the real number. the results are: 7 6 5 4 3 2 1 0 h e x 11 0 11 101 dd 01 110 0 0 1 71 0 0 0 1 0 0 1 0 12
m icroprocessor z ilog 8-bit load group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ld r,r r ? r x x 01 r r 1 2 ld r,n r ? n x x 00 r 110 2 2 ?? n ?? ld xyu,n xyu ? n x x 11 y11 101 3 2 00 100 110 26 ?? n ?? ld xyl,n xyl ? n x x 11 y11 101 3 2 00 101 110 2e ?? n ?? ld r,(hl) r ? (hl) x x 01 r 110 1 2+r ld r,(xy+d) r ? (xy+d) x x 11 y11 101 3 4+r i 01 r 110 ?? d ?? ld (hl),r (hl) ? r x x 01 110 r 1 3+w ld (xy+d),r (xy+d) ? r x x 11 y11 101 3 5+w i 01 110 r ?? d ?? ld (hl),n (hl) ? n x x 00 110 110 36 2 3+w ?? n ?? ld (xy+d),n (xy+d) ? n x x 11 y11 101 4 5+w i 00 110 110 36 ?? d ?? ?? n ?? ld a,(bc) a ? (bc) x x 00 001 010 0a 1 2+r ld a,(de) a ? (de) x x 00 011 010 1a 1 2+r ld a,(nn) a ? (nn) x x 00 111 010 3a 3 3+r i ?? n ?? ?? n ?? ld (bc),a (bc) ? a x x 00 000 010 02 1 3+w ld (de),a (de) ? a x x 00 010 010 12 1 3+w ld (nn),a (nn) ? a x x 00 110 010 32 3 4+w i ?? n ?? ?? n ??
m icroprocessor z ilog 8-bit load group (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ld xyu,s xyu ? s x x 11 y11 101 2 2 01 100 s ld xyl,s xyl ? s x x 11 y11 101 2 2 01 101 s ld s,xyu s ? xyu x x 11 y11 101 2 2 01 s 100 ld s,xyl s ? xyl x x 11 y11 101 2 2 01 s 101 ld a,i a ? i x 0 x ief 0 11 101 101 ed 2 2 01 010 111 57 ld a,r a ? r x 0 x ief 0 11 101 101 ed 2 2 01 011 111 5f ld i,a i ? a x x 11 101 101 ed 2 2 01 000 111 47 ld r,a r ? a x x 11 101 101 ed 2 2 01 001 111 4f r , r r e g s r e g s y x y 000 b 000 b 0 ix 001 c 001 c 1 iy 010 d 010 d 011 e 011 e 100 h 100 ixu (x = 0),iyu(x = 1) 101 l 101 ixl (x = 0),iyl(x = 1) 111 a 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions.
m icroprocessor z ilog 16/32 bit load group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ld dd,nn dd ? nn x x 00 dd0 001 3 2 l1,i ?? n ?? ?? n ?? ld xy,nn xy ? nn x x 11 y11 101 4 2 l1,i 00 100 001 21 ?? n ?? ?? n ?? ld hl,(nn) h ? (nn+1) x x 00 101 010 2a 3 3+r l1,i l ? (nn) ?? n ?? ?? n ?? ld dd,(nn) ddh ? (nn+1) x x 11 101 101 ed 4 3+r l1,i ddl ? (nn) 01 dd1 011 ?? n ?? ?? n ?? ld xy,(nn) xyu ? (nn+1) x x 11 y11 101 4 3+r l1,i xyl ? (nn) 00 101 010 2a ?? n ?? ?? n ?? ld (nn),hl (nn+1) ? h x x 00 100 010 22 3 4+w l1,i (nn) ? l ?? n ?? ?? n ?? ld (nn),dd (nn+1) ? ddh x x 11 101 101 ed 4 4+w l1,i (nn) ? ddl 01 dd0 011 ?? n ?? ?? n ?? ld (nn),xy (nn+1) ? xyu x x 11 y11 101 4 4+w l1,i (nn) ? xyl 00 100 010 22 ?? n ?? ?? n ?? ld w(pp),nn (pp+1) ? nh x x 11 101 101 ed 4 3+w l1,i (pp) ? nl 00 pp0 110 ?? n ?? ?? n ?? ld pp,(uu) pph ? (uu+1) x x 11 011 101 dd 2 2+r l1 ppl ? (uu) 00 pp1 1uu ld (pp),uu (pp+1) ? uuh x x 11 111 101 fd 2 3+w l1 (pp) ? uul 00 pp1 1uu ld sp,hl sp ? hl x x 11 111 001 f9 1 2 l1 ld sp,xy sp ? xy x x 11 y11 101 2 2 l1 11 111 001 f9 ld pp,uu pp ? uu x x 11 uu1 101 2 2 l1 00 pp0 010 ld xy,pp xy ? pp x x 11 y11 101 2 2 l1 00 pp0 111 ld ix,iy ix ? iy x x 11 011 101 dd 2 2 l1 00 100 111 27
m icroprocessor z ilog 16/32 bit load group (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ld iy,ix iy ? ix x x 11 111 101 fd 2 2 l1 00 100 111 27 ld pp,xy pp ? xy x x 11 y11 101 2 2 l1 00 pp1 011 ld (pp),xy (pp+1) ? xyu x x 11 y11 101 2 3+w l1 (pp) ? xyl 00 pp0 001 ld xy,(pp) xyu ? (pp+1) x x 11 y11 101 2 2+r l1 xyl ? (pp) 00 pp0 011 ld pp,(xy+d) pph ? (xy+d)h x x 11 y11 101 4 4+r l1,i ppl ? (xy+d)l 11 001 011 cb ?? d ?? 00 pp0 011 ld ix,(iy+d) ixu ? (iy+d)h x x 11 111 101 fd 4 4+r l1,i ixl ? (iy+d)l 11 001 011 cb ?? d ?? 00 100 011 23 ld iy,(ix+d) iyu ? (ix+d)h x x 11 011 101 dd 4 4+r l1,i iyl ? (ix+d)l 11 001 011 cb ?? d ?? 00 100 011 23 ld pp,(sp+d) pph ? (sp+d)h x x 11 011 101 dd 4 4+r l1,i ppl ? (sp+d)l 11 001 011 cb ?? d ?? 00 pp0 001 ld xy,(sp+d) xyu ? (sp+d)h x x 11 y11 101 4 4+r l1, i xyl ? (sp+d)l 11 001 011 cb ?? d ?? 00 100 001 21 ld (xy+d),pp (xy+d)h ? pph x x 11 y11 101 4 5+w l1, i (xy+d)l ? ppl 11 001 011 cb ?? d ?? 00 pp1 011 ld (ix+d),iy (ix+d)h ? iyu x x 11 011 101 dd 4 5+w l1, i (ix+d)l ? iyl 11 001 011 cb ?? d ?? 00 101 011 2b ld (iy+d),ix (iy+d)h ? ixu x x 11 111 101 fd 4 5+w l1, i (iy+d)l ? ixl 11 001 011 cb ?? d ?? 00 101 011 2b
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ld (sp+d),pp (sp+d)h ? pph x x 11 011 101 dd 4 5+w l1, i (sp+d)l ? ppl 11 001 011 cb ?? d ?? 00 pp1 001 ld (sp+d),xy (sp+d)h ? xyu x x 11 y11 101 4 5+w l1, i (sp+d)l ? xyl 11 001 011 cb ?? d ?? 00 101 001 29 ld [w] i,hl i ? hl x x 11 011 101 dd 2 2 l1 01 000 111 47 ld [w] hl,i hl ? i x x 11 011 101 dd 2 2 l1 01 010 111 57 d d p a i r q q p a i r p p , u u p a i r y x y 00 bc 00 bc 00 bc 0 ix 01 de 01 de 01 de 1 iy 10 hl 10 hl 11 hl 11 sp 11 af notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. l1: in long word mode, this instruction loads in 32 bits; dst(31-0) ? src(31-0)
m icroprocessor z ilog push/pop instructions symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes push qq (sp-2) ? qql x x 11 qq0 101 1 3+w n,l2,l4 (sp-1) ? qqh sp ? sp-2 push xy (sp-2) ? xyl x x 11 y11 101 2 3+w n, l2 (sp-1) ? xyu 11 100 101 e5 sp ? sp-2 push nn (sp-2) ? nnl x x 11 111 101 fd 4 3+w n, l4,i (sp-1) ? nnh 11 110 101 f5 sp ? sp-2 ?? n ?? ?? n ?? push sr (sp-2) ? sr(7-0) x x 11 101 101 ed 2 3+w n, l2 (sp-1) ? sr(15-8) 11 000 101 c5 sp ? sp-2 pop qq qqh ? (sp+1) x x 11 qq0 001 1 2+r n, l3, l5 qql ? (sp) sp ? sp+2 pop xy xyu ? (sp+1) x x 11 y11 101 2 1+r n, l3 xyl ? (sp) 11 100 001 e1 sp ? sp+2 pop sr sr(6-0) ? (sp) x x 11 101 101 ed 2 3+r n, l6 sr(15-8) ? (sp+1) 11 000 001 c1 sr(23-16) ? (sp+1) sr(31-24) ? (sp+1) sp ? sp+2 q q p a i r y x y 00 bc 0 ix 01 de 1 iy 10 hl 11 af notes: instructions in italic face are z380 new instructions, instructions with underline are z180 original instructions. i: this instruction may be used with ddir immediate instructions. l2: in long word mode, this instruction pushes the registers extended portion (register with z suffix) before pushing the contents of the register to the stack. l3: in long word mode, this instruction pops the registers extended portion (register with z suffix) after popping the contents of the register to the stack. l4: in long word mode, push af and push nn instructions push 0000h onto stack in the place of the extended register portion. l5: in long word mode, pop af instruction increments sp by two after poping 1 word of data from stack. l6: in long word mode, this instruction pops one more word from stack and loads into sr(31-16), instead of duplicating (sp+1) location into sr(31- 16). n: in native mode, this instruction uses addresses modulo 65536. (10): in case of af register pair, execute time is one clock less.
m icroprocessor z ilog exchange, block transfer, block search groups symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ex af, af sr(0) ? not sr(0) x x 00 001 000 08 1 3 ex de,hl de(15-0) ? hl(15-0) x x 11 101 011 eb 1 3 l7 ex bc,de bc(15-0) ? de(15-0) x x 11 101 101 ed 2 3 l7 00 000 101 05 ex bc,hl bc(15-0) ? hl(15-0) x x 11 101 101 ed 2 3 l7 00 001 101 0d exx sr(8) ? not sr(8) x x 11 011 001 d9 1 3 ex (sp),hl h ? (sp+1) x x 11 100 011 e3 1 3+r+w n ,l7 l ? (sp) ex (sp),xy xyu ? (sp+1) x x 11 y11 101 2 3+r+w n ,l7 xyl ? (sp) 11 100 011 e3 ex a,r a ? r x x 11 101 101 ed 2 3 00 r 111 ex a,(hl) a ? (hl) x x 11 101 101 ed 2 3+r+w 00 110 111 37 ex r,r r ? r x x 11 001 011 cb 2 3 00 110 r ex pp,pp pp(15-0) ? pp(15-0) x x 11 101 101 ed 3 3 l7 11 001 011 cb 00 110 0pp ex xy,xy xy(15-0) ? xy(15-0) x x 11 101 101 ed 3 3 l7 11 001 011 cb 00 110 10y ex pp,xy pp(15-0) ? xy(15-0) x x 11 101 101 ed 2 3 l7 00 ppy 011 ex ix,iy ix(15-0) ? iy(15-0) x x 11 101 101 ed 2 3 l7 00 101 011 2b exall sr(24) ? not sr(24) x x 11 101 101 ed 2 3 sr(16) ? not sr(16) 11 011 001 d9 sr(8) ? not sr(8) exxx sr(16) ? not sr(16) x x 11 011 101 dd 2 3 11 011 001 d9 exxy sr(24) ? not sr(24) x x 11 111 101 fd 2 3 11 011 001 d9 swap pp pp(31-16) ? pp(15-0) x x 11 101 101 ed 2 2 00 pp1 110 swap xy xy(31-16) ? xy(15-0) x x 11 y11 101 2 2 00 111 110 3e ldi (de) ? (hl) x 0 x v 0 11 111 101 fd 2 3+r+w n de ? de+1 (1) 10 100 000 a0 hl ? hl+1 bc(15-0) ? bc(15-0)-1 ldir (de) ? (hl) x 0 x 0 0 11 101 101 ed 2 (3+r+w)n n de ? de+1 (2) 10 110 000 b0 hl ? hl+1 bc(15-0) ? bc(15-0)-1 repeat until bc = 0 ldd (de) ? (hl) x 0 x v 0 11 101 101 ed 2 3+r+w n de ? de-1 (1) 10 101 000 a8 hl ? hl-1 bc(15-0) ? bc(15-0)-1
m icroprocessor z ilog exchange, block transfer, block search groups (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes lddr (de) ? (hl) x 0 x 0 0 11 101 101 ed 2 (3+r+w)n n de ? de-1 (2) 10 111 000 b8 hl ? hl-1 bc(15-0) ? bc(15-0)-1 repeat until bc = 0 cpi a-(hl) x x v 1 11 101 101 ed 2 3+r n (3) (1) 10 100 001 a1 hl ? hl+1 bc(15-0) ? bc(15-0)-1 cpir a-(hl) x x 0 1 11 101 101 ed 2 (3+r)n n (3) (2) 10 110 001 b1 hl ? hl+1 bc(15-0) ? bc(15-0)-1 repeat until a = (hl) or bc = 0 cpd a-(hl) x x v 1 11 101 101 ed 2 3+r n (3) (1) 10 101 001 a9 hl ? hl-1 bc(15-0) ? bc(15-0)-1 cpdr a-(hl) x x 0 1 11 101 101 ed 2 (3+r)n n (3) (2) 10 111 001 b9 hl ? hl-1 bc(15-0) ? bc(15-0)-1 repeat until a = (hl) or bc = 0 ldiw (de) ? (hl) x 0 x v 0 11 101 101 ed 2 (3+r+w)n n,l8(4) (de+1) ? (hl+1) (1) 11 100 000 e0 de ? de+2 hl ? hl+2 bc(15-0) ? bc(15-0)-2 ldirw (de) ? (hl) x 0 x 0 0 11 101 101 ed 2 (3+r+w)n n,l8(4) (de+1) ? (hl+1) (2) 11 110 000 f0 de ? de+2 hl ? hl+2 bc(15-0) ? bc(15-0)-2 repeat until bc = 0
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes lddw (de) ? (hl) x 0 x v 0 11 101 101 ed 1 3+r+w n,l8(4) (de+1) ? (hl+1) (1) 11 101 000 e8 de ? de-2 hl ? hl-2 bc(15-0) ? bc(15-0)-2 lddrw (de) ? (hl) x 0 x 0 0 11 101 101 ed 1 (3+r+w)nn,l8(4) (de+1) ? (hl+1) (2) 11 111 000 f8 de ? de-2 hl ? hl-2 bc(15-0) ? bc(15-0)-2 repeat until bc = 0 r r e g p p r e g s y x y 000 b 00 bc 0 ix 001 c 00 de 1 iy 010 d 11 hl 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. l7: in long word mode, this instruction exchanges in 32-bits; src(31-0) ? dst(31-0) l8: in long word mode, this instruction transfers in 2 words and bc modified by 4 instead of 2 n: in native mode, this instruction uses addresses modulo 65536. (1): p/v flag is 0 if the result of bc-1 = 0, otherwise p/v = 1. (2): p/v flag is 0 only at completion of instruction. (3): z flag is 1 if a = (hl), otherwise z = 0 (4): source, destination address, count value must be even numbers.
m icroprocessor z ilog 8-bit arithmetic and logical group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes add a,r a ? a + r x x v 0 10 (000) r 1 2 add a,n a ? a + n x x v 0 11 (000) 110 2 2 ?? n ?? add a,(hl) a ? a + (hl) x x v 0 10 (000) 110 1 2+r add a,(xy+d) a ? a + (xy + d) x x v 0 11 y11 101 3 4+r i 10 (000) 110 ?? d ?? add a,xyu a ? a + xyu x x v 0 11 y11 101 2 2 10 (000) 100 add a,xyl a ? a + xyl x x v 0 11 y11 101 2 2 10 (000) 101 adc a,s a ? a + s + cy x x v 0 (001) sub s a ? a - s x x v 1 (010) sbc a,s a ? a - s - cy x x v 1 (011) and s a ? a and s x 1 x p 0 0 (100) or s a ? a or s x 0 x p 0 0 (110) xor s a ? a xor s x 0 x p 0 0 (101) cp s a - s x x v 1 (111) s is any of r, n, xyu, xyl, (hl), (ix+d), (iy+d) as shown for add instruction. the indicated bits replace the (000) in the add set above. incr r ? r + 1 x x v 0 00 r (100) 1 2/3 (5) inc (hl) (hl) ? (hl) + 1 x x v 0 00 110 (100) 1 2+r+w inc (xy+d) (xy + d) ? (xy + d) + 1 x x v 0 11 y11 101 3 4+r+w i 00 110 (100) ?? d ?? inc xyu xyu ? xyu + 1 x x v 0 11 y11 101 2 2 00 100 (100) inc xyl xyl ? xyl + 1 x x v 0 11 y11 101 2 2 00 101 (100) dec m m ? m - 1 x x v 1 (101) m is any of r, xyu, xyl, (hl), (ix+d), (iy+d) as shown for inc instructions. the indicated bits replace (100) with (101) in operand.
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes t s t r a and r x 1 x p 0 0 11 101 101 ed 2 2 00 r 100 t s t n a and n x 1 x p 0 0 11 101 101 ed 3 2 01 100 100 64 ?? n ?? t s t ( h l ) a and (hl) x 1 x p 0 0 11 101 101 ed 2 2+r 00 110 100 34 r r e g y x y 000 b 0 ix 001 c 1 iy 010 d 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. (5): two cycles to execute for accumulator, three cycles to execute for any other registers.
m icroprocessor z ilog general purpose arithmetic and cpu control group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes daa @ x x p 00 100 111 27 1 3 cpl[a] a ? not a x 1 x 1 00 101 111 2f 1 2 ones complement cplw[hl] hl ? not hl x 1 x 1 11 011 101 dd 2 2 ones complement 00 101 111 2f neg[a] a ? 0-a x x v 1 11 101 101 ed 1 2 twos complement 01 000 100 44 negw[hl] hl ? 0-hl x x v 1 11 101 101 ed 1 2 twos complement 01 010 100 54 exts [a] l ? a x x 11 101 101 ed 2 3 l9 h ? 00 if d7 = 0 01 100 101 65 h ? ff if d7 = 1 extsw [hl] hlz ? 0000 if h[7] = 0 x x 11 101 101 ed 3 hlz ? ffff if h[7] = 1 01 110 101 75 ccf cy ? not cy x x 0 00 111 111 3f 1 2 complement carry flag scf cy ? 1 x 0 x 0 1 00 110 111 37 1 2 nop no operation x x 00 000 000 00 1 2 halt cpu halted x x 01 110 110 76 1 2 s l p sleep x x 11 101 101 ed 2 2 01 110 110 76 di # sr(5) ? 0 x x 11 110 011 f3 1 2 di n # ier(i) ? 0 if n(i) = 1 x x 11 011 101 dd 3 2 sr(5) ? 0 if n(0) = 1 11 110 011 f3 ?? n ?? ei # sr(5) ? 1 x x 11 111 011 fb 1 2 ei n # ier(i) ? 1 if n(i) = 1 x x 11 011 101 dd 3 2 sr(5) ? 1 if n(0) = 1 11 111 011 fb ?? n ?? im 0 set int mode 0 x x 11 101 101 ed 2 4 01 000 110 46 im 1 set int mode 1 x x 11 101 100 ed 2 4 01 010 101 56 im 2 set int mode 2 x x 11 101 101 ed 2 4 01 011 110 5e im 3 set int mode 3 x x 11 101 101 ed 2 4 01 001 110 4e ldctl sr,a sr(31-24) ? a x x 11 011 101 dd 2 4 sr(23-16) ? a 11 001 000 c8 sr(15-8) ? a ldctl sr,n sr(31-24) ? n x x 11 011 101 dd 3 4 sr(23-16) ? n 11 001 010 ca sr(15-8) ? n ?? n ?? ldctl hl,sr hl(15-0) ? sr(15-0) x x 11 101 101 ed 2 2 l1 11 000 000 c0
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ldctl sr,hl sr(15-8) ? hl(15-8) x x 11 101 101 ed 2 4 l1 sr(0) ? hl(0) 11 001 000 c8 if (lw) sr(31-16) ? hl(31-16) else sr(31-24) ? hl(15-8) sr(23-16) ? hl(15-8) ldctl a,v v ? a x x 11 vv1 101 2 2 11 010 000 d0 ldctl v,a a ? v x x 11 vv1 101 2 4 11 011 000 d8 ldctl v,n v ? n x x 11 vv1 101 3 4 11 011 010 da ?? n ?? setc lck sr(1) ? 1 x x 11 101 101 ed 2 4 set lock mode 11 110 111 f7 setc lw sr(6) ? 1 x x 11 011 101 dd 2 4 set long word mode 11 110 111 f7 setc xm sr(7) ? 1 x x 11 111 101 fd 2 4 set extend mode 11 110 111 f7 resc lck sr(1) ? 0 x x 11 101 101 ed 2 4 reset lock mode 11 111 111 ff resc lw sr(6) ? 0 x x 11 011 101 dd 2 4 reset long word mode 11 111 111 ff btest bank test x x 11 101 01 ed 2 2 s ? sr(16) 11 001 111 cf z ? sr(24) v ? sr(0) c ? sr(8) mtest mode test x x 11 011 101 dd 2 2 s ? sr(7) 11 001 111 cf z ? sr(6) c ? sr(1) v v c o n t r o l r e g s 01 xsr 10 dsr 11 ysr notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. l1: in long word mode, this instruction loads in 32 bits; dst(31-0) ? src(31-0) l9: in long word mode, this instruction operates in 32-bits; if a(7) = 0 then hl(31-16) = 0000h else ffffh @: converts accumulator content into packed bcd following add or subtract with packed bcd operands. #: interrupts are not sampled at the end of ei and di.
m icroprocessor z ilog decoder directive instructions opcode # of execute mnemonic operation 76 543 210 hex bytes time notes ddir w operate following inst in word mode. 11 011 101 dd +2 0 11 000 000 c0 ddir ib,w operate following inst in word mode. 11 011 101 dd +3 0 fetching additional byte data. 11 000 001 c1 ddir iw,w operate following inst in word mode. 11 011 101 dd +4 0 fetching additional word data. 11 000 010 c2 ddir ib fetching additional byte data. 11 011 101 dd +3 0 11 000 011 c3 ddir lw operate following inst in long word mode. 11 111 101 fd +2 0 11 000 000 c0 ddir ib,lw operate following inst in long word mode. 11 111 101 fd +3 0 fetching additional byte data. 11 000 001 c1 ddir iw,lw operate following inst in word mode. 11 111 101 fd +4 0 fetching additional word data. 11 000 010 c2 ddir iw fetching additional word data. 11 111 101 fd +4 0 11 000 011 c3
m icroprocessor z ilog 16/32 bit arithmetic and logical group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes add hl,dd hl ? hl+ dd x x 0 00 dd1 001 1 2 x1 adc hl, dd hl ? hl+ dd + cy x x v 0 11 101 101 ed 2 2 01 dd1 010 sbc hl,dd hl ? hl - dd - cy x x v 1 11 101 101 ed 2 2 01 dd0 010 add xy,qq xy ? xy + qq x x 0 11 y11 101 2 2 x1 00 qq1 001 add xy,xy xy ? xy + xy x x 0 11 y11 101 2 x1 00 101 001 29 inc[w] dd dd ? dd + 1 x x 00 dd0 011 1 2 x1 inc[w] xy xy ? xy + 1 x x 11 y11 101 2 2 x1 00 100 011 23 dec[w] dd dd ? dd - 1 x x 00 dd1 011 1 2 x1 dec[w] xy xy ? xy - 1 x x 11 y11 101 2 2 x1 00 101 011 2b add sp,nn sp ? sp + nn x x 0 11 101 101 ed 4 2 x1, i 10 000 010 82 ?? n ?? ?? n ?? sub sp,nn sp ? sp - nn x x 1 11 101 101 ed 4 2 x1, i 10 010 010 92 ?? n ?? ?? n ?? addw [hl,]pp hl ? hl + pp x x v 0 11 101 101 ed 2 2 10 (000) 1pp
m icroprocessor z ilog 16/32 bit arithmetic and logical group (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes addw [hl,]nn hl ? hl + nn x x v 0 11 101 101 ed 4 2 i 10 (000) 110 86 ?? n ?? ?? n ?? addw [hl,]xy hl ? hl+xy x x v 0 11 y11 101 2 2 i 10 (000) 111 87 addw [hl,](xy+d) hl ? hl+(xy+d) x x v 0 11 y11 101 4 4+r i 11 (000) 110 c6 adcw [hl,]uu hl ? hl+uu+cy x x v 0 (001) subw [hl,]uu hl ? hl-uu x x v 1 (010) sbcw [hl,]uu hl ? hl - uu - cy x x v 1 (011) andw [hl,]uu hl ? hl and uu x 1 x p 0 0 (100) orw [hl,]uu hl ? hl or uu x 0 x p 0 0 (110) xorw [hl,]uu hl ? hl xor uu x 0 x p 0 0 (101) cpw [hl,]uu hl - uu x x v 1 (111) add hl, (nn) hl ? hl+(nn) x x 0 11 101 101 ed 4 2+r i, x1 11 010 110 c6 ?? n ?? ?? n ?? sub hl, (nn) hl ? hl- (nn) x x 0 11 101 101 ed 4 2+r i, x1 11 010 110 d6 ?? n ?? ?? n ?? uu is any of rr, nn, t, (ix+d), (iy+d) as shown for addw instruction. the indicated bits replace the (000) is the add set above. d d p a i r p p p a i r q q p a i r y x y 00 bc 00 bc 00 bc 0 ix 01 de 01 de 01 de 1 iy 10 hl 11 hl 11 sp 11 sp notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. x1: in extend mode, this instruction operates in 32-bits; src(31-0) ? src(31-0) opr dst(31-0)
m icroprocessor z ilog multiply/divide instruction group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes m l t d d dd ? ddh * ddl x x 11 101 101 ed 2 7 01 dd1 100 multw [hl,]pp hl(31-0) x x 0 11 101 101 ed 3 10 ? hl(15-0) * pp(15-0) 11 001 011 cb 10 (010) 0pp multw [hl,]xy hl(31-0) x x 0 11 101 101 ed 3 10 ? hl(15-0) * xy(15-0) 11 001 011 cb 10 (010) 10y multw [hl,]nn hl(31-0) x x 0 11 101 101 ed 5 10 i ? hl(15-0) * nn 11 001 011 cb 10 (010) 111 97 ?? n ?? ?? n ?? multw (xy+d) hl(31-0) x x 0 11 y11 101 4 12+r i ? hl(15-0) * (xy+d) 11 001 011 cb ?? d ?? 10 (010) 010 92 multuw uu hl(31-0) x x 0 (011) ? hl(15-0) * uu multuw uu instructions, uu is any of pp, nn, xy, (nn), (xy+d) as shown for multw instruction with replacing (010) by (010). execute time is time required for mutw with one more clock.
m icroprocessor z ilog multiply/divide instruction group (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes divuw [hl,]pp hl(15-0) 0 x x v 11 101 101 ed 3 20 i ? hl(31-0)/pp 11 001 011 cb hl(31-16) ? remainder 10 111 0pp ?? d ?? divuw [hl,]xy hl(15-0) 0 x x v 11 101 101 ed 3 20 ? hl(31-0)/xy 11 001 011 cb hl(31-16) ? remainder 10 111 10y divuw [hl,]nn hl(15-0) 0 x x v 11 101 101 ed 5 20 ? hl(31-0)/nn 11 001 011 cb hl(31-16) ? remainder 10 111 111 bf ?? n ?? ?? n ?? divuw [hl,](xy+d) hl(15-0) 0 x x v 11 y11 101 4 22+r i ? hl(31-0)/(xy+d) 11 001 011 cb hl(31-16) ? remainder ?? d ?? 10 111 010 ba r r e g p p r e g s y x y d d r e g s 000 b 00 bc 0 ix 00 bc 001 c 00 de 1 iy 01 de 010 d 11 hl 10 hl 011 e 11 sp 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions.
m icroprocessor z ilog 8-bit rotate and shift group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes rlca rotate left circular x 0 x 0 00 000 111 07 1 2 accumulator rla rotate left accumulator x 0 x 0 00 010 111 17 1 2 rrca rotate right circular x 0 x 0 00 001 111 0f 1 2 accumulator rra rotate right accumulator x 0 x 0 00 011 111 1f 1 2 rlc r rotate left circular x 0 x p 0 11 001 011 cb 2 2 register r 00 (000) r rlc (hl) rotate left circular x 0 x p 0 11 001 011 cb 2 2+r 00 (000) 110 06 rlc (xy+d) rotate left circular x 0 x p 0 11 y11 101 4 4+r i 11 001 011 cb ?? d ?? 00 (000) 110 rl m rotate left x 0 x p 0 (010) rrc m rotate right circular x 0 x p 0 (001) rr m rotate right x 0 x p 0 (011) sla m shift left arithmetic x 0 x p 0 (100) sra m shift right arithmetic x 0 x p 0 (101) srl m shift right logical 0 x 0 x p 0 (111) above instructions format and states are as shown for rlcs. to form new opcode replace (000) of rlcs with shown code. rld rotate left digit x 0 x p 0 11 101 101 ed 2 3+r (6) between the accumulator 01 101 111 6f and location (hl) rrd rotate right digit x 0 x p 0 11 101 101 ed 2 3+r (6) between the accumulator 01 100 111 67 and location (hl) r r e g p p r e g s y x y 000 b 00 bc 0 ix 001 c 00 de 1 iy 010 d 11 hl 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. (6): the contents of the upper half of the accumulator is unaffected.
m icroprocessor z ilog 16/32 bit rotate and shift group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes rlcw pp rotate left circular x 0 x p 0 11 101 101 ed 3 2 11 001 011 cb 00 (000) 0pp rlcw xy rotate left circular x 0 x p 0 11 101 101 ed 3 2 11 001 011 cb 00 (000) 10y rlcw (hl) rotate left circular x 0 x p 0 11 101 101 ed 3 2+r 11 001 011 cb 00 (000) 010 rlcw (xy+d) rotate left circular x 0 x p 0 11 y11 101 4 4+r i 11 001 011 cb ?? d ?? 00 (000) 010 rlw m rotate left x 0 x p 0 (010) rrcw m rotate right circular x 0 x p 0 (001) rrw m rotate right x 0 x p 0 (011) slaw m shift left arithmetic x 0 x p 0 (100) sraw m shift right arithmetic x 0 x p 0 (101) srlw m shift right logical 0 x 0 x p 0 (111) instruction format and states are as shown for rlcw. to form new opcode replace (000) or rlcw with shown code. p p r e g s y x y 00 bc 0 ix 00 de 1 iy 11 hl notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions.
m icroprocessor z ilog 8-bit bit set, reset, and test group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes bit b,r z ? rb x 1 x 0 11 001 011 cb 2 01 b r bit b,(hl) z ? (hl)b x 1 x 0 11 001 011 cb 2 01 b 110 bit b,(xy+d) z ? (xy+d)b x 1 x 0 11 y11 101 4 i 11 001 011 cb ?? d ?? 01 b 110 set b,r rb ? 1 x x 11 001 011 cb 2 (11) b r set b,(hl) (hl)b ? 1 x x 11 001 011 cb 2 (11) b 110 set b,(xy+d) (xy+d)b ? 1 x x 11 y11 101 4 i 11 001 011 cb ?? d ?? (11) b 110 res b,m mb ? 0 (10) to form new opcode replace (11) of set b,s with (10). s is any of r,(hl), (xy+d). the notation mb indicates location m, bit b(0~7) r r e g y x y 000 b 0 ix 001 c 1 iy 010 d 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be operate with ddir immediate instructions.
m icroprocessor z ilog jump group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes jp nn pc(15-0) ? nn x x 11 000 011 c3 3 2 x2, i ?? n ?? ?? n ?? jp (hl) pc(15-0) ? hl(15-0) x x 11 101 001 e9 1 2 x2 jp (xy) pc(15-0) ? xy(15-0) x x 11 y11 101 2 2 x2 11 101 001 e9 jp cc,nn if condition cc is true x x 11 cc 010 3 2 x2, i then pc ? nn ?? n ?? otherwise continue ?? n ?? jr e pc ? pc + e x x 00 011 000 18 2 2 n, (7) ?? e-2 ?? jr c,e if c = 0 continue x x 00 111 000 38 2 2 n, (7) if c = 1, pc ? pc + e ?? e-2 ?? jr nc,e if c = 1 continue x x 00 110 000 30 2 2 n, (7) if c = 0, pc ? pc + e ?? e-2 ?? jr z,e if z = 0 continue x x 00 101 000 28 2 2 n, (7) if z = 1, pc ? pc + e ?? e-2 ?? jr nz,e if z = 1 continue x x 00 100 000 20 2 2 n, (7) if z = 0, pc ? pc + e ?? e-2 ?? jr ee pc ? pc + ee x x 11 011 101 dd 4 2 n, (8) 00 011 000 18 ? (ee-4)l ? ? (ee-4)h ? jr c,ee if c = 0 continue x x 11 011 101 dd 4 2 n, (8) if c = 1, pc ? pc + ee 00 111 000 38 ? (ee-4)l ? ? (ee-4)h ? jr nc,ee if c = 1 continue x x 11 011 101 dd 4 2 n, (8) if c = 0, pc ? pc + ee 00 110 000 30 ? (ee-4)l ? ? (ee-4)h ? jr z,ee if z = 0 continue x x 11 011 101 dd 4 2 n, (8) if z = 1, pc ? pc + ee 00 101 000 28 ? (ee-4)l ? ? (ee-4)h ? jr nz,ee if z = 1 continue x x 11 011 101 dd 4 2 n, (8) if z = 0, pc ? pc + ee 00 100 000 20 ? (ee-4)l ? ? (ee-4)h ? jr eee pc ? pc + eee x x 11 111 101 fd 5 2 n, (9) 00 011 000 18 ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ? jr c,eee if c = 0 continue x x 11 111 101 fd 5 2 n, (9) if c = 1, pc ? pc + eee 00 111 000 38 ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ?
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes jr nc,eee if c = 1 continue x x 11 111 101 fd 5 2 n, (9) if c = 0, pc ? pc + eee 00 110 000 30 ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ? jr z,eee if z = 0 continue x x 11 111 101 fd 5 2 n, (9) if z = 1, pc ? pc + eee 00 101 000 28 ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ? jr nz,eee if z = 1 continue x x 11 111 101 fd 5 2 n, (9) if z = 0, pc ? pc + eee 00 100 000 20 ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ? djnz e b ? b - 1 x x 00 010 000 10 2 3/4 n, (7) if b = 0 continue ? e-2 ? if b ? 0, pc ? pc + e djnz ee b ? b - 1 x x 11 011 101 dd 4 3/4 n, (8) if b = 0 continue 00 010 000 10 if b 1 0, pc ? pc + ee ? (ee-4)l ? ? (ee-4)h ? djnz eee b ? b - 1 x x 11 111 101 fd 5 3/4 n, (9) if b = 0 continue 00 010 000 10 if b 1 0, pc ? pc + eee ? (eee-5)l ? ? (eee-5)m ? ? (eee-5)h ? c c c o n d i t i o n 000 nz (non-zero) 001 z (zero) 010 nc (non-carry) 011 c (carry) 100 po (parity odd), or nv (non-overflow) 101 pe (parity even), or v (overflow) 110 p (sign positive), or ns (no sign) 111 m (sign negative), or s (sign) notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. n: in native mode, this instruction uses addresses modulo 65536. x2: in extend mode, this instruction loads bit 31-16 portion of the operand into pc(31-16). (7): e is a signed twos complement number in the range [-126, 129], e-2 in the opcode provides an effective address of pc+e as pc is incremented by 2 prior to the addition of e. (8): ee is a signed twos complement number in the range [-32765, 32770], ee-4 in the opcode provides an effective address of pc+e as pc is incremented by 4 prior to the addition of e. (9): eee is a signed twos complement number in the range [-8388604, 8388611], eee-5 in the opcode provides an effective address of pc+e as pc is incremented by 5 prior to the addition of e.
m icroprocessor z ilog call and return group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes call nn (sp-1) ? pch x x 11 001 101 cd 3 4+w x3, i (sp-2) ? pcl ?? n ?? sp ? sp-2 ?? n ?? pc ? nn call cc,nn if condition cc x x 11 cc 100 3 2/4+w x3, i is false continue ?? n ?? otherwise same as call nn ?? n ?? calr e (sp-1) ? pch x x 11 101 101 ed 3 4+w n,x3,(11) (sp-2) ? pcl 11 001 101 cd sp ? sp-2 pc ? pc + e ?? e-3 ?? calr cc,e if condition cc x x 11 101 101 ed 3 2/4+w n,x3,(11) is false continue 11 cc 100 otherwise same as calr e ?? e-3 ?? calr ee (sp-1) ? pch x x 11 011 101 dd 4 4+w n,x3,(8) (sp-2) ? pcl 11 001 101 cd sp ? sp-2 ? (ee-4)l ? pc ? pc + ee ? (ee-4)h ? calr cc,ee if condition cc x x 11 011 101 dd 4 2/4+w n,x3,(8) is false continue 11 cc 100 otherwise same as ? (ee-4)l ? calr ee ? (ee-4)h ? calr eee (sp-1) ? pch x x 11 111 101 fd 5 4+w n,x3,(9) (sp-2) ? pcl 11 001 101 cd sp ? sp-2 ? (eee-5)l ? pc ? pc + eee ? (eee-5)m ? ? (eee-5)h ? calr cc,eee if condition cc x x 11 111 101 fd 5 2/4+w n,x3,(9) is false continue 11 cc 100 otherwise same as ? (eee-5)l ? calr eee ? (eee-5)m ? ? (eee-5)h ? ret pcl ? (sp) x x 11 001 001 c9 1 2+r n, x4 pch ? (sp + 1) sp ? sp+2 ret cc if condition cc x x 11 cc 000 1 2/2+r n, x4 is false continue otherwise same as ret reti return from interrupt x x 11 101 101 ed 2 2+r n, x4 01 001 101 4d
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes retn return from nmi x x 11 101 101 ed 2 2+r n,x4,(10) 01 000 101 45 rst p (sp-1) ? pch x x 11 t 111 1 4+w n,x3,x5 (sp-2) ? pcl sp ? sp-2 pch ? 0 pcl ? p c c c o n d i t i o n t p 000 nz (non-zero) 000 00h 001 z (zero) 001 08h 010 nc (non-carry) 010 10h 011 c (carry) 011 18h 100 po (parity odd), or nv (non-overflow) 100 20h 101 pe (parity even), or v (overflow) 101 28h 110 p (sign positive), or ns (no sign) 110 30h 111 m (sign negative), or s (sign) 111 38h notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. n: in native mode, this instruction uses addresses modulo 65536. x3: in extended mode, this instruction pushes pc(31-16) into the stack before pushing pc(15-0) into the stack. x4: in extended mode, this instruction pops pc(31-16) from the stack after poping pc(15-0) from the stack. x5: in extended mode, this instruction loads 00h into pc(31-16). (2) in extended mode, all return instructions pops pcz from the stack after poping pc from the stack. (8): ee is a signed twos complement number in the range [-32765, 32770], ee-4 in the opcode provides an effective address of pc+e as pc is incremented by 4 prior to the addition of e. (9): eee is a signed twos complement number in the range [-8388604, 8388611], eee-5 in the opcode provides an effective address of pc+e as pc is incremented by 5 prior to the addition of e. (10) retn loads iff2 to iff1. (11): e is a signed twos complement number in the range [-127, 128], e-3 in the opcode provides an effective address of pc+e as pc is incremented by 3 prior to the addition of e.
m icroprocessor z ilog 8-bit input and output group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes in a,(n) a ? (n) x x 11 011 011 db 2 3+i ?? n ?? in r,(c) r ? (c) x 0 x p 0 11 101 101 ed 2 01 r 000 ina a,(nn) a ? (nn) x x 11 101 101 ed 2 3+i i 11 011 011 db ?? n ?? ?? n ?? ini (hl) ? (c) x x 1 11 101 101 ed 2 2+i+w b ? b - 1 (1) 10 100 010 a2 hl ? hl + 1 inir (hl) ? (c) 1 x x 1 11 101 101 ed 2 (2+i+w) b ? b-1 (2) 10 110 010 b2 hl ? hl + 1 repeat until b = 0 ind (hl) ? (c) x x 1 11 101 101 ed 2 2+i+w b ? b - 1 (1) 10 101 010 aa hl ? hl - 1 indr (hl) ? (c) 1 x x 1 11 101 101 ed 2 (2+i+w)n b ? b-1 (2) 10 111 010 ba hl ? hl - 1 repeat until b = 0 out (n),a (n) ? a x x 11 010 011 d3 2 3+o ?? n ?? out (c),r (c) ? r x x 11 101 101 ed 2 3+o 01 r 001 out (c),n (c) ? r x x 11 101 101 ed 3 3+o 01 110 001 71 ?? n ?? outa (nn),a (nn) ? a x x 11 101 101 ed 4 2+o i 11 010 011 d3 ?? n ?? ?? n ??
m icroprocessor z ilog symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes outi b b-1 x x 1 11 101 101 ed 2 2+r+o n (c) ? (hl) (1) 10 100 011 a3 hl ? hl + 1 otir b ? b-1 1 x x 1 11 101 101 ed 2 2+r+o n (c) ? (hl) (2) 10 110 011 b3 hl hl + 1 repeat until b = 0 outd b ? b-1 1 x x 1 11 101 101 ed 2 2+r+o n (c) ? (hl) (2) 10 111 011 bb hl hl - 1 repeat until b = 0 otdr b ? b-1 1 x x 1 11 101 101 ed 2 2+r+o n (c) ? (hl) (2) 10 111 011 bb hl hl - 1 repeat until b = 0 r r e g 000 b 001 c 010 d 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. n: in native mode, this instruction address modulo 65536. (1): p/v flag is 0 if the result of bc-1 = 0, otherwise p/v = 1/. (2): p/v flag is 0 only at completion of instruction.
m icroprocessor z ilog input and output instructions for on-chip i/o space symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes ino r,(n) r ? (n) x 0 x p 0 11 101 101 ed 3 3+i (3) 00 r 000 ?? n ?? ino (n) r ? (n) x 0 x p 0 11 101 101 ed 3 3+i (3) changes flag only. 00 r 000 30 ?? n ?? out0 (n),r (n) ? r x x 11 101 101 ed 3 3+o (3) 00 r 001 ?? n ?? tstio n (c) and n x 1 x p 0 0 11 101 101 ed 3 3+i (3) 01 110 100 74 ?? n ?? otiim (c) ? (hl) x x p 11 101 101 ed 3 2+r+o (3),n hl ? hl + 1 10 000 011 83 c ? c+1 b ? b - 1 otiimr (c) ? (hl) 0 1 x 0 x 1 0 11 101 101 ed 3 2+r+o (3),n hl ? hl + 1 (2) 10 010 011 93 c ? c + 1 b ? b -1 repeat until b = 0 otdm (c) ? (hl) x x p 11 101 101 ed 3 2+r+o (3),n hl ? hl - 1 10 001 011 8b c ? c - 1 b ? b - 1 otdmr (c) ? (hl) 0 1 x 0 x 1 0 11 101 101 ed 3 2+r+o (3),n hl ? hl - 1 (2) 10 011 011 9b c ? c - 1 b ? b - 1 repeat until b = 0 r r e g 010 d 011 e 100 h 101 l 111 a notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. n: in native mode, this instruction address modulo 65536. (1): p/v flag is 0 if the result of bc-1 = 0, otherwise p/v = 1/. (2): p/v flag is 0 only at completion of instruction.
m icroprocessor z ilog 16-bit input and output group symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes inw pp,(c) pp ? (c) x 0 x p 0 11 011 101 dd 2 01 ppp 000 inaw hl,(nn) hl(15-0) ? (nn) x x 11 111 101 fd 4 3+i i 11 011 011 db ?? n ?? ?? n ?? iniw (hl) ? (de) x x 1 11 101 101 ed 2 2+i+w n bc(15-0) ? bc(15-0) - 1 (1) 11 100 010 e2 hl ? hl+2 inirw (hl) ? (de) 1 x x 1 11 101 101 ed 2 (2+i+w)n n bc(15-0) ? bc(15-0) - 1 (2) 11 110 010 f2 hl ? hl+2 repeat until bc = 0 indw (hl) ? (de) x x 1 11 101 101 ed 2 2+i+w n bc(15-0) ? bc(15-0) - 1 (1) 11 101 010 ea hl ? hl - 2 indrw (hl) ? (de) 1 x x 1 11 101 101 ed 2 (2+i+w)n n bc(15-0) ? bc(15-0) - 1 (2) 11 111 010 fa hl ? hl - 2 repeat until bc = 0 outw (c),pp (c) ? pp x x 11 011 101 dd 2 2+o 01 ppp 001 outw (c),nn (c) ? nn x x 11 111 101 fd 4 2+o 01 111 001 79 ?? n ?? ?? n ?? outaw (nn),hl (nn) ? hl(15-0) x x 11 111 101 fd 4 2+o i 11 010 011 d3 ?? n ?? ?? n ?? outiw (de) ? (hl) x x 1 11 101 101 ed 2 2+o n bc(15-0) ? bc(15-0) - 1 (1) 11 100 011 e3 hl ? hl + 2 otirw bc(15-0) ? bc(15-0) - 1 1 x x 1 11 101 101 ed 2 2+o n (de) ? (hl) (2) 11 110 011 f3 hl ? hl + 2 repeat until b = 0
m icroprocessor z ilog 16-bit input and output group (continued) symbolic flags p/ opcode # of execute mnemonic operation s z x h x v n c 76 543 210 hex bytes time notes outdw bc(15-0) ? bc(15-0) - 1 x x 1 11 101 101 ed 2 2+r+o (de) ? (hl) (1) 11 101 011 eb hl ? hl - 2 otdrw bc(15-0) ? bc(15-0) - 1 1 x x 1 11 101 101 ed 2 2+r+o (de) ? (hl) (2) 11 111 011 fb hl ? hl - 2 repeat until b = 0 p p p r e g 000 bc 010 de 111 hl notes: instructions in italic face are z380 new instructions, instructions with u n d e r l i n e are z180 original instructions. i: this instruction may be used with ddir immediate instructions. n: in native mode, this instruction uses addresses modulo 65536. (1) if the result of b-1 is zero, the z flag is set; otherwise it is reset. (2) z flag is set upon instruction completion only. address bus i/o instruction a31-a24 a23-a16 a15-a8 a7-a0 in a, (n) 00000000 00000000 contents of a reg n in dst,(c) bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 ina(w) dst,(mn) 00000000 00000000 m n ddir ib ina(w) dst,(lmn) 00000000 l m n ddir iw ina(w) dst,(klmn) k l m n block input bbc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 out (n),a 00000000 00000000 contents of a reg n out (c),dst bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0 outa(w) (mn),dst 00000000 00000000 m n ddir ib outa(w) (lmn),dst 00000000 l m n ddir iw outa(w) (klmn),dst k l m n block output bc31-bc24 bc23-bc16 bc15-bc8 bc7-bc0
m icroprocessor z ilog interrupts the z380 mpus interrupt structure provides compatibility with the existing z80 and z180 mpus with the following exception: the undefined opcode traps occurrence is with respect to the z380 instruction set, and its response is improved (vs the z180) to make trap handling easier. the z380 mpu also offers additional features to enhance flexibility in system design. of the five external interrupt inputs provided, the /nmi is a nonmaskable interrupt. the remaining inputs, /int3-/int0, are four asynchronous maskable interrupt requests. in an interrupt acknowledge transaction, address outputs a31-a0 are driven to logic 1's. one output among a3-a0 is driven to logic 0 to indicate the maskable interrupt request being acknowledged. if /int0 is being acknowledged, a3-a1, is at logic 1's and a0 is at logic 0. interrupt modes 0 through 3 are supported for the external maskable interrupt request /int0. modes 0, 1 and 2 have the same schemes as those in the z80 and z180 mpus. mode 3 is similar to mode 2, except that 16-bit interrupt vectors are expected from the i/o devices. note that 8-bit and 16-bit i/o devices can be intermixed in this mode by having external pull up resistors at the data bus signals d15-d8, for example. the external maskable interrupt requests /int3-/int1 are handled in an assigned interrupt vectors mode. as discussed in the cpu architecture section, the z380 mpu can operate in either the native or extended mode. in native mode, pushing and poping of the stack to save and retrieve interrupted pc values in interrupt handling are done in 16-bit sizes, and the stack pointer rolls over at the 64 kbyte boundary. in extended mode, the pc pushes and pops are done in 32-bit sizes, and the stack pointer rolls over at the 4 gbyte memory space boundary. the z380 mpu provides an interrupt register extension, whose contents are always outputted as the address bus signals a31-a16 when fetching the starting addresses of service routines from memory in interrupt modes 2, 3 and the assigned vectors mode. in native mode, such fetches are automatically done in 16-bit sizes and in extended mode, in 32-bit sizes. these starting addresses should be even- aligned in memory locations. that is, their least significant bytes should have addresses with a0 = 0. interrupt priority ranking the z380 mpu assigns a fixed priority ranking to handle its interrupt sources, as shown in table 2. table 2. interrupt priority ranking priority interrupt sources highest trap (undefined opcode) /nmi /int0 /int1 /int2 lowest /int3
m icroprocessor z ilog the on-chip i/o address space and can be accessed only with reserved on-chip i/o instructions. table 3. interrupt flags and registers names mnemonics access methods interrupt enable flags ief1, ief2 ei and di instructions interrupt register i ld i,a and ld a,i instructions interrupt register extension iz ld i,hl and ld hl,i instructions (accessing both iz and i) interrupt enable register ier on-chip i/o instructions, addr 00000017h, ei and di instructions assigned vectors base register avbr on-chip i/o instructions, addr 00000018h trap and break register trpbk on-chip i/o instructions, addr 00000019h interrupt control the z380 mpus flags and registers associated with inter- rupt processing are listed in table 4. as discussed in the cpu architecture section, some of the registers reside in ief1, ief2 ief1 controls the overall enabling and disabling of all on- chip peripheral and external maskable interrupt requests. if ief1 is at logic 0, all such interrupts are disabled. the purpose of ief2 is to correctly manage the occurrence of /nmi. when /nmi is acknowledged, the state of ief1 is copied to ief2 and then ief1 is cleared to logic 0. at the end of the /nmi interrupt service routine, execution of the return from nonmaskable interrupt instruction, retn, automatically copies the state of ief2 back to ief1. this is a means to restore the interrupt enable condition existing before the occurrence of /nmi. table 5 summarizes the states of ief1 and ief2 resulting from various operations. table 4. operation effects on ief1 and ief2 operation ief1 ief2 comments /reset 0 0 inhibits all interrupts except trap and /nmi. trap 0 0 disables interrupt nesting. /nmi 0 ief1 ief1 value copied to ief2, then ief1 is cleared. retn ief2 nc returns from /nmi service routine. /int3-/int0 0 0 disables interrupt nesting. reti nc nc returns from service routine, z80 i/o device. ret nc nc returns from service routine, non-z80 i/o device. ei 1 1 di 0 0 ld a,i or ld r,i nc nc ief2 value is copied to p/v flag. ld hl,i nc nc note: nc = no change i, i extend the 8-bit interrupt register and the 16-bit interrupt register extension are cleared during reset.
m icroprocessor z ilog interrupt enable register ie3-ie0 (interrupt request enable flags). these flags individually indicate f /int3, /int2, /int1 or /int0 is enabled. note that these flags are conditioned with enable and disable interrupt instructions (with arguments). reserved bits 7-4. read as 0s, should write to as 0s. figure 25. interrupt enable register assigned vectors base register ab15-ab9 (assigned vectors base). the interrupt regis- ter extension, iz, together with ab15-ab9, define the base address of the assigned interrupt vectors table in memory space (figure 26). reserved bit 0. read as 0, should write to as 0. ab15 7 ab14 ab13 ab12 ab11 ab10 ab9 -- 0 0 00 0 0 00 0 reset value avbr : 00000018h r/w assigned vectors base reserved program as 0 read as 0 figure 26. assigned vectors base register -- 7 ie1 ie0 1 0 00 0 0 00 0 reset value ier : 00000017h read only interrupt requests enable encoded interrupt requests -- -- -- ie2ie3
m icroprocessor z ilog trap and break register reserved bits 7-2. some of these bits are reserved for breakpoint functions, including a break-on-halt feature. refer to the z380 ice specifications for details. read as 0s, should write to as 0s. 7 tf tv 0 00 0 0 00 0 0 reset value trpbk : 00000019h r/w trap on interrupt vector reserved program as 0 read as 0 -- -- -- -- trap on instruction fetch -- -- figure 27. trap and break register tf (trap on instruction fetch). tf goes active to logic 1 when an undefined opcode fetched in the instruction stream is detected. tf can be reset under program control by writing it with a logic 0. however, it cannot be written with a logic 1. tv (trap on interrupt vector). tv goes active to logic 1 when an undefined opcode is returned as a vector in an interrupt acknowledge transaction in mode 0. tv can be reset under program control by writing it with a logic 0. however, it cannot be written with a logic 1. trap interrupt the z380 mpu generates a trap when an undefined opcode is encountered. the trap is enabled immediately after reset, and it is not maskable. this feature can be used to increase software reliability or to implement extended instructions. an undefined opcode can be fetched from the instruction stream, or it can be returned as a vector in an interrupt acknowledge transaction in interrupt mode 0. when a trap occurs, the z380 mpu operates as follows. 1. the tf or tv bit in the assigned vectors base and trap register goes active, to indicate the source of the undefined opcode. 2. if the undefined opcode was fetched from instruction stream, the starting address of the trap causing in- struction is pushed onto the stack. (note that the starting address of a decoder directive preceding an instruction encoding is considered the starting ad- dress of the instruction.) if the undefined opcode was a returned interrupt vector (in interrupt mode 0), the interrupted pc value is pushed onto the stack. 3. the states of ief1 and ief2 are cleared. 4. the z380 mpu commences to fetch and execute instructions from address 00000000h. note that instruction execution resumes at address 0, similar to the occurrence of a reset. testing the tf and tv bits in the assigned vectors base and trap register will distinguish the two events. even if trap handling is not in place, repeated restarts from address 0 is an indicator of possible illegal instructions at system debugging.
m icroprocessor z ilog nonmaskable interrupt the nonmaskable interrupt input /nmi is edge sensitive, with the z380 mpu internally latching the occurrence of its falling edge. when the latched version of /nmi is recog- nized, the following operations are performed. 1. the interrupted pc (program counter) value is pushed onto the stack. 2. the state of ief1 is copied to ief2, then ief1 is cleared. 3. the z380 mpu commences to fetch and execute in- structions from address 00000066h. interrupt mode 0 response for maskable interrupt /int0 during the interrupt acknowledge transaction, the external i/o device being acknowledged is expected to output a vector onto the lower portion of the data bus, d7-d0. the z380 mpu interprets the vector as an instruction opcode, which is usually one of the single-byte restart (rst) instructions that pushes the interrupted pc (program counter) value onto the stack and resumes execution at a fixed memory location. however, the z380 mpu will gen- erate multiple transactions to capture vectors that form a multi-byte instruction. ief1 and ief2 are reset to logic 0s, disabling all further maskable interrupt requests. note that unlike the other interrupt responses, the pc is not automati- cally pushed onto the stack. note also that a trap occurs if an undefined opcode is supplied by the i/o device as a vector. interrupt mode 1 response for maskable interrupt /int0 an interrupt acknowledge transaction is generated, during which the data bus contents are ignored by the z380 mpu. the interrupted pc value is pushed onto the stack. ief1 and ief2 are reset to logic 0s so as to disable further maskable interrupt requests. instruction fetching and ex- ecution restarts at memory location 00000038h. interrupt mode 2 response for maskable interrupt /int0 during the interrupt acknowledge transaction, the external i/o device being acknowledged is expected to output a vector onto the lower portion of the data bus, d7-d0. the interrupted pc value is pushed onto the stack and ief1 and ief2 are reset to logic 0s so as to disable further maskable interrupt requests. the z380 mpu then reads an entry from a table residing in memory and loads it into the pc to resume execution. the address of the table entry is composed of the i extend contents as a31-a16, the i register contents as a15-a8 and the vector supplied by the i/o device as a7-a0. note that the table entry is effectively the starting address of the interrupt service routine designed for the i/o device being acknowledged. the table, composed of starting addresses for all the interrupt mode 2 service routines, can be referred to as the interrupt mode two vector table. each table entry should be word-sized if the z380 mpu is in the native mode and longword-sized if in the extended mode, in either case it is even-aligned (least significant byte with address a0 = 0). interrupt mode 3 response for maskable interrupt /int0 interrupt mode 3 is similar to mode 2 except that a 16-bit vector is expected to be placed on the data bus d15-d0 by the i/o device during the interrupt acknowledge transac- tion. the interrupted pc is pushed onto the stack. ief1 and ief2 are reset to logic 0s so as to disable further maskable interrupt requests. the starting address of the service routine is fetched and loaded into the pc to resume execution from the memory location with an address composed of the i extend contents as a31-a16 and the vector supplied by the i/o device as a15-a0. again the starting address of the service routine is word-sized if the z380 mpu is in the native mode and longword-sized if in the extend mode, in either case even-aligned.
m icroprocessor z ilog assigned interrupt vectors mode for maskable interrupt int3-/int1 when the z380 mpu recognizes one of the external maskable interrupts it generates an interrupt acknowl- edge transaction which is different than that for /int0. the interrupt acknowledge transaction for /int3-/int1 has the i/o bus signal /intak active, with /mi, /iorq, /iord and/ iowr inactive. the interrupted pc value is pushed onto the stack. ief1 and ief2 are reset to logic 0s, disabling further maskable interrupt requests. the starting address of an interrupt service routine is fetched from a table entry and loaded into the pc to resume execution. the address of the table entry is composed of the i extend contents as a31-a16, the ab bits of the assigned vectors base reg- ister as a15-a9 and an assigned interrupt vector specific to the request being recognized as a8-a0. the assigned vectors are defined in table 5. table 5. assigned interrupt vectors interrupt source assigned interrupt vector /int1 00h /int2 04h /int3 08h reti instruction the z80 family i/o devices are designed to monitor the return from interrupt opcodes in the instruction stream (reti-edh, 4dh), signifying the end of the current inter- rupt service routine. when detected, the daisy chain within and among the device(s) resolves and the appropriate interrupt-under-service condition clears. the z380 mpu reproduces the opcode fetch transactions on the i/o bus when the reti instruction is executed. note that the z380 mpu outputs the reti opcodes onto both portions of the data bus (d15-d8 and d7-d0) in the transactions.
m icroprocessor z ilog on-chip peripheral functions the z380 mpu incorporates a number of functions to ease its interface with external i/o devices and with various types of memories. the z380 mpu's i/o bus can be programmed to run at a slower rate than its memory bus. in addition, a heartbeat transaction can be generated on the i/o bus that emulates a z80 cpu instruction fetch cycle. such a transaction is useful for a particular z80 family i/o device to perform its interrupt functions. memory chip select signals can be activated to access the lowest 16 mbytes of the z380 mpu's memory address space, with wait state insertions. lastly, a dram refresh function is incorporated, with programmable refresh transaction burst size. the above functions are controlled by several on- chip registers. as described in the cpu architecture section, these registers together with several other regis- ters that control a portion of the interrupt functions, occupy an on-chip i/o address space. this on-chip i/o address can be accessed only by the following reserved on-chip i/o instructions. some on-chip peripherals are capable of generating inter- rupt requests, which are always handled in the assigned interrupt vectors mode. i/o bus control the z380 mpu is designed to interface easily with external i/o devices that can be of either the z80 or z8500 product family by supplying five i/o bus control signals: /m1, /iorq, /iord, /iowr and /intak. in addition, the z380 mpu is supplying an ioclk that is a divided down version of its busclk. programmable wait states can be inserted in the various i/o transactions. the external interface section details all the i/o transactions. in0 r, (n) otim in0 (n) otimr out0 (n), r otdm tstio n otdmr when one of the above instructions is executed, the z380 mpu outputs the register address being accessed in a pseudo transaction of two busclk cycles duration, with the address signals a31-a8 at logic 0s. in the pseudo transaction, all bus control signals are at their inactive states. it is to be emphasized that the z380 mpu adopts an instruction specific scheme to access on-chip i/o regis- ters, with their unique address space. this is in contrast to mapping such registers with external peripherals in a common i/o address space, as is done in the z180 mpu. i/o bus control register 0 cr2-cr0 (i/o clock rate). busclk is divided down to produce ioclk as defined in the following. 000 divided-by-8 001 divided-by-1 010 divided-by-2 011 divided-by-1 100 divided-by-4 101 divided-by-1 110 divided-by-6 111 divided-by-1 note that if a clock divide rate of 1 is specified, busclk should be used to connect to i/o devices that require a clock input, since the z380 mpu outputs a constant logic 1 at ioclk. reserved bits 7-3. read as 0s, should write to as 0s. 7 cr2 cr1 cr0 0 00 0 0 00 0 0 <- reset value iocr0 : 00000011h r/w - - - - - - - - - - i/o clock reserved program as 0 read as 0 figure 28. i/o bus control register 0
m icroprocessor z ilog i/o bus control register 1 when this phantom register iocr1 with address 00000012h is accessed with one of the on-chip i/o write instructions, a heartbeat transaction that emulates a z80 cpu instruction fetch is performed on the i/o bus. this transaction provides a /m1 pulse which is necessary as part of an interrupt enable sequence for a z80 pio product. in the on-chip i/o write instruction, the data being "written" can be of any value. in case of an on-chip i/o read with the iocr1 address, the data returned is unpredictable. i/o waits register ow2-iow0 (i/o waits). this binary field defines up to seven wait states to be inserted in external i/o read and write transactions, and at the latter portions of interrupt transactions to capture interrupt vectors. the defined wait states are also inserted in each of the opcode fetch transactions of the return from interrupt (reti) instruction reproduced on the i/o bus. when programmed with 0s, the i/o waits are disabled. rtw1-rtw0 (reti waits). this binary field defines up to three wait states to be inserted between opcode fetch transactions of the return from interrupt instruction repro- duced on the i/o bus. dcw2-dcw0 (interrupt daisy chain waits). this binary field defines up to seven wait states to be inserted at the early portions of interrupt acknowledge transactions, for the interrupt daisy chain through the external i/o devices to settle. figure 29. i/o waits register iow2 7 iow1 iow0 rtw1 rtw0 dcw2 dcw1 dcw0 1 11 1 1 11 1 0 <- reset value iowr : 0000000eh r/w interrupt daisy chain waits ret i waits i/o waits
m icroprocessor z ilog memory chip selects and waits the z380 mpu offers two schemes to generate chip select signals to access the lowest 16 mbytes of its memory address space. the first scheme provides six chip select signals, with the address space partitioned as shown in figure 30. the second scheme provides three chip select signals, and the address space partitioning is shown in figure 31. note that the /mcs0 signal is used to indicate accesses to the entire mid-range memory in the second scheme. a flexible wait state insertion scheme is incorporated in the chip select logic. a user can program t1, t2 and t3 waits separately for accesses to the lower, upper and mid-range memory areas. if chip select scheme one is in effect, different wait states can be defined for each of the mid- range memory areas 3 through 0. 00ffffff upper memory mid-range memory3 mid-range memory2 mid-range memory1 mid-range memory0 lower memory /umcs /mcs3 /mcs2 /mcs1 /mcs0 /lmcs 00000000 memory chip select scheme 1 unused unused figure 30. chip select address space 00ffffff upper memory mid-range memory lower memory /umcs /mcs /lmcs 00000000 memory chip select scheme 2 figure 31. chip select address space
m icroprocessor z ilog lower memory chip select control this memory area has its lower boundary at address 000000000h. a user can define the size to be an integer power of two, starting at 4 kbytes. for example, the lower memory area can be either 4 kbytes, 8 kbytes, 16 kbytes, etc., starting from address 0. the /lmcs signal can be enabled to go active during refresh transactions. lower memory chip select register 0 ma15-ma12 (match address bits 15-12). if a match ad- dress bit is at logic 1, the corresponding address signal of a memory transaction is compared for a logic 0, as a condition for /lmcs to become active. if the match ad- dress bit is at logic 0, the corresponding address signal is not compared (don't care). for example, ma12 deter- mines if a12 should be tested for a logic 0 in memory transactions. reserved bits 3-1. read as 0s, should write to as 0s. erf (enable for refresh transactions). if this bit is pro- grammed to a logic one, /lmcs goes active during refresh transactions. ma15 7 ma14 ma13 ma12 - - erf 0 00 0 0 00 0 0 <- reset value lmcsr0 : 00000000h r/w reserved program as 0 read as 0 match address bits 15-12 - - - - enable for refresh figure 32. lower memory chip select register 0 lower memory chip select register 1 ma23-ma16 (match address bits 23-16). if a match address bit is at logic 1, the corresponding address signal of a memory transaction is compared for a logic 0, as a condition for /lmcs to become active. if the match address bit is at logic 0, the corresponding address signal is not compared (don't care). for example, ma23 deter- mines if a23 should be tested for a logic 0 in memory transactions. note that in order for /lmcs to go active in a memory transaction, the /lmcs function has to be enabled in the memory selects master enable register (described later), all the address signals a31-a24 at logic 0s, and all the address signals a23-a12 programmed for address matching in the above registers have to be at logic 0s. to define the lower memory area as 4 kbytes, ma23-ma12 should be programmed with 1s. for an area larger than 4 kbytes, ma23-ma12 (in that order) should be programmed with contiguous 1s followed by contiguous 0s. this is the intended usage to maintain the lower memory area as a single block. note also that /lmcs can be enabled for refresh transactions independent of the value programmed into the memory selects master enable register. 7 ma23 ma22 ma21 1 11 0 1 00 0 0 <- reset value lmcsr1 : 00000001h r/w ma20 ma19 ma18 ma17 ma16 match address bits 23-16 figure 33. lower memory chip select register 1
m icroprocessor z ilog upper memory chip select control the upper boundary for this memory area is address 00ffffffh. a user can define the area immediately below this boundary with a size that is an integer power of two, starting at 4 kbytes. that is, the upper memory area can be either 4 kbytes, 8 kbytes, 16 kbytes and so on. the /umcs signal can be enabled to go active during refresh transac- tions. upper memory chip select register 0 ma15-ma12 (match address bits 15-12). if a match ad- dress bit is at logic 1, the corresponding address signal of a memory transaction is compared for a logic 1, as a condition for /umcs to become active. if the match ad- dress bit is at logic 0, the corresponding address signal is not compared (don't care). for example, ma12 deter- mines if a12 should be tested for a logic 1 in memory transactions. reserved bits 3-1. read as 0s, should write to as 0s. erf (enable for refresh transactions). if this bit is pro- grammed to a logic 1, /umcs goes active during refresh transactions. 7 ma15 ma14 ma13 0 00 0 0 00 0 0 <- reset value umcsr0 : 00000002h r/w ma12 erf enable for refresh - - - - - - reserved program as 0 read as 0 match address bits 15-12 upper memory chip select register 1 ma23-ma16 (match address bits 23-16). if a match ad- dress bit is at logic 1, the corresponding address signal of a memory transaction is compared for a logic 1, as a condition for /umcs to become active. if the mask address bit is at logic 0, the corresponding address signal is not compared (don't care). for example, ma23 determines if a23 should be tested for a logic 1 in memory transactions. note that in order for/umcs to go active in a memory transaction, the /umcs function has to be enabled in the memory selects master enable register (described later), all the address signals a31-a24 at logic 0s, and all the address signals a23-a12 programmed for address match- ing in the above registers have to be at logic 1s. to define the upper memory area as 4 kbytes, ma23-ma12 should be programmed with 1s. for an area larger than 4 kbytes, ma23-ma12 (in that order) should be programmed with contiguous 1s followed by contiguous 0s. this is the intended usage to maintain the upper memory area as a single block. note also that /umcs can be enabled for refresh transactions independent of the value programmed into the memory selects master enable register. ma23 7 ma22 ma21 ma20 ma19 ma18 ma17 ma16 1 11 0 1 00 0 0 <- reset value umcsr1 : 00000003h r/w match address bits 23-16 figure 34. upper memory chip select register 0 figure 35. upper memory chip select register 1
m icroprocessor z ilog mid-range memory chip select register 1 ma23-ma16 (match address bits). in chip select scheme 1, if a match address bit is at logic 1, the corresponding address signal of a memory transaction is compared with the corresponding base address bit for a match, as a condition for one of /mcs3-/mcs0 to become active. if the match address bit is at logic 0, the corresponding address signal and base address bit are not compared (don't care). for example, ma23 determines if a23 should be compared for a match with ba23. the contents of this register have no effects in chip select scheme 2. mid-range memory chip select(s) control in chip select scheme 1, a user can define the base address and the total size of the mid-range memory area. the /mcs0 signal would be active for the lowest quarter portion of the area defined, starting from the base address. each of the /mcs1-/mcs3 signals would be active, corre- sponding to the successively higher quarter portions of the total mid-range memory area. in chip select scheme 2, the mid-range memory area is between the lower and upper memory areas. the /mcs3-/mcs0 signals can be individu- ally enabled to go active in refresh transactions. mid-range memory chip select register 0 ma15-ma14 (match address bits 15-14). in chip select scheme 1, if a match address bit is at logic 1, the corre- sponding address signal of a memory transaction is com- pared with the corresponding base address bit for a match, as a condition for one of /mcs3-/mcs0 to become active. if the match address bit is at logic 0, the corre- sponding address signal and base address bit are not compared (don't care). for example, ma14 determines if a14 should be compared for a match with ba14. the values of ma15-ma14 have no effects in chip select scheme 2. reserved bits 5-4. read as 0s, should write to as 0s. erf3-erf0 (enable for refresh transactions). the mid- range memory chip select signals can be individually enabled to go active during refresh transactions. as an example, /mcs0 goes active in refresh transactions if erf0 is programmed at logic 1. figure 36. mid-range memory chip select register 0 ma15 7 ma14 - - - - erf3 erf2 erf1 erf0 0 00 0 0 00 0 0 <- reset value mmcsr0 : 00000004h r/w enable for refresh transactions reserved bits match address bits 15-14 ma23 7 ma22 ma21 ma20 ma19 ma18 ma17 ma16 0 00 0 0 00 0 0 <- reset value mmcsr1 : 00000005h r/w match address bits 23-16 figure 37. mid-range memory chip select register 1 mid-range memory chip select register 2 & 3 figure 38. mid-range memory chip select register 2 ba15 7 ba14 0 00 0 0 00 0 0 <- reset value mmcsr2 : 00000006h r/w -- -- -- -- -- --
m icroprocessor z ilog ba23-ba14 (base address 23-14). in chip select scheme 1, the address signals a23-a16 of a memory transaction are compared with ba23-ba16 for a match, for those bits programmed for address matching in the mid-range memory chip select register 1. the contents of this register have no effects in chip select scheme 2. note that in order for one of /mcs3-/mcs0 to go active in a memory transaction in chip select scheme 1, the enm1 bit in the memory selects master enable register (described later) has to be at logic 1, all the address signals a31-a24 at logic 0s, and for those bits programmed for address matching, a23-a14 matching ba23-ba14. for the intended usage to maintain the mid-range memory area as a single block, ma23-ma14 (in that order) should be programmed for address matching with contiguous 1s followed by contigu- ous 0s. note also that /mcs3-/mcs0 can be individually enabled to go active during refresh transactions, indepen- dent of the value programmed into the memory selects master enable register. ba23 7 ba22 ba21 ba20 ba19 ba18 ba17 ba16 0 00 0 0 00 0 0 <- reset value mmcsr3 : 00000007h r/w figure 39. mid-range memory chip select register 3 lower memory wait register t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions access- ing the lower memory area. t2w1-t2w0 (t2 wait states). this binary field defines up to three t2 wait states to be inserted in transactions accessing the lower memory area. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the lower memory area. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value lmwr : 00000008h r/w t3 waits t2 waits t1 waits figure 40. lower memory waits register upper memory wait register t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions access- ing the upper memory area. t2w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in transactions access- ing the upper memory area. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the upper memory area. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value umwr : 00000009h r/w t3 waits t2 waits t1 waits figure 41. upper memory waits register
m icroprocessor z ilog mid-range memory wait register 0 t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions accessing the mid-range memory area 0 in chip select scheme 1, or the entire mid-range memory area in chip select scheme 2. t2w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in transactions access- ing the mid-range memory area 0 in chip select scheme 1, or the entire mid-range memory area in chip select scheme 2. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the mid-range memory area 0 in chip select scheme 1, or the entire mid-range memory area in chip select scheme 2. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value mmwr0 : 0000000ah r/w t3 waits t2 waits t1 waits mid-range memory wait register 1 t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions accessing the mid-range memory area 1 in chip select scheme 1. t2w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in transactions access- ing the mid-range memory area 1 in chip select scheme 1. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the mid-range memory area 1 in chip select scheme 1. the contents of this register have no effects in chip select scheme 2. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value mmwr1 : 0000000bh r/w t3 waits t2 waits t1 waits figure 43. mid-range memory waits register 1 figure 42. mid-range memory waits register 0
m icroprocessor z ilog mid-range memory wait register 2 t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions accessing the mid-range memory area 2 in chip select scheme 1. t2w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in transactions access- ing the mid-range memory area 2 in chip select scheme 1. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the mid-range memory area 2 in chip select scheme 1. the contents of this register have no effects in chip select scheme 2. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value mmwr2 : 0000000ch r/w t3 waits t2 waits t1 waits figure 44. mid-range memory waits register 2 mid-range memory waits register 3 t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in transactions accessing the mid-range memory area 3 in chip select scheme 1. t2w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in transactions access- ing the mid-range memory area 3 in chip select scheme 1. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in transactions access- ing the mid-range memory area 3 in chip select scheme 1. the contents of this register have no effects in chip select scheme 2. t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value mmwr3 : 0000000dh r/w t3 waits t2 waits t1 waits figure 45. mid-range memory waits register 3
m icroprocessor z ilog memory chip selects and waits master control the memory chip selects and their associated waits are enabled or disabled by writing to a single register de- scribed in the following: memory selects master enable register a user can set or reset the desired bits 7-4 in this register without modifying the states of the remaining bits, with the sr bit defining the set or reset function. enlm (enable lower memory chip select and waits). this bit at logic 1 enables the /lmcs signal to go active starting at t1 cycle time of a memory transaction accessing the lower memory area. the associated programmed wait states are automatically inserted in the transaction. enum (enable upper memory chip select and waits). this bit at logic 1 enables the /umcs signal to go active starting at t1 cycle time of a memory transaction access- ing the upper memory area. the associated programmed wait states are automatically inserted in the transaction. enm1 (enable mid-range memory chip select scheme 1 and waits). this bit at logic 1 enables one of /mcs3- /mcs0 to go active starting at t1 cycle time of a memory transaction, depending on which of the mid-range memory areas 3-0 is being accessed. the corresponding pro- grammed wait states are automatically inserted in the transaction. enm2 (enable mid-range memory chip select scheme 2 and waits). this bit at logic 1 enables the /mcs0 to go active starting at t1 cycle time of a memory transaction accessing the mid-range memory area. the correspond- ing programmed wait states are automatically inserted in the transaction. reserved bits 3-1. read as 0s, should write to as 0s. figure 46. memory selects master enable register enlm 7 enum enm1 enm2 -- -- -- sr 1 01 0 0 00 0 0 <- reset value msmer : 00000010h r/w enable lower memory chip select and waits enable upper memory chip select and waits enable mid-range memory chip select scheme 1 and waits enable mid-range memory chip select scheme 2 and waits set reset control reserved sr (set reset control). when writing to the memory selects master enable register with sr = 1, bits 7-4 that are selected with logic 1s are set. when writing with sr = 0, bits 7-4 that are selected with logic 1s are cleared. in either case, the bits not selected are not modified. the sr bit is always read as a logic 0. additional comments. in either chip select scheme, if the chip select and waits functions are enabled, or their memory areas are defined to cause overlaps, the prece- dence of conflict resolution is /lmcs, then /umcs, then /mcs3-/mcs0. as an example, consider the case where both the lower and mid-range memory area 0 are defined to occupy the same address space. with enlm = 1 in the memory selects master enable register (enm1 can be either 0 or 1), /lmcs goes active in the memory transaction that accesses the overlapped address space. with enlm = 0 and enm1 = 1, /mcs0 would go active in the transaction instead. regardless of the state of the address bus, the chip select signals are at their inac- tive logic 1s when the corresponding enable bits in the memory selects master enable register (msmer) are at logic 0s, except during dram refresh transactions if so enabled, or the z380 mpus cpu is in its halt state, except during dram refresh transactions if so enabled, or the z380 mpu relinquishes the system bus with its /breq input active, or the z380 mpu is in the low power standby mode.
m icroprocessor z ilog dram refresh the z380 mpu is capable of providing refresh transactions to dynamic memories that have internal refresh address counters. a user can select how often refresh requests should be made to the z80 mpu's external interface logic, as well as the burst size (number of refresh transactions) for each request iteration. the external interface logic grants these requests by performing refresh transactions with cas-before-ras timing on the /trefr, /trefa and /trefc bus control signals. in these transactions, /bhen, /blen and the user specified chip select signal(s) are driven active to facilitate refreshing all the dram modules at the same time. a user can also specify the t1, t2 and t3 waits to be inserted. note that the z380 mpu cannot provide refresh transactions when it relinquishes the sys- tem bus, with its /breq input active. in that situation, the number of missed refresh requests are accumulated in a counter, and when the z80 mpu regains the system bus, the missed refresh transactions will be performed. refresh register 0 ri7-ri0 (request interval). ri7-ri0 defines the interval between refresh requests to the z380 mpu's external interface logic. a value n specified in this field denotes the request interval to be (4 x n) busclk periods. if ri7-ri0 are programmed as 0s, the request interval is 1024 busclk periods. ri7 7 ri6 ri5 ri4 ri3 ri2 ri1 ri0 0 00 0 0 00 0 0 <- reset value rfshr0 : 00000013h r/w request interval figure 47. refresh register 0 refresh register 1 mr7-mr0 (missed requests count). this count incre- ments by 1 when a refresh request is made, to a maximum value of 255. refresh requests over the maximum value would be lost. when the z380 mpu's external interface logic completes each burst of refresh transactions, the count decrements by 1. a user can read the count status, and if necessary, take corrective actions such as adjusting the burst size. when refresh function is disabled, this count is held at 0. mr7 7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 0 00 0 0 00 0 0 <- reset value rfshr1 : 00000014h r only missed requests count figure 48. refresh register 1
m icroprocessor z ilog refresh register 2 rfen (refresh enable). enables the refresh function when programmed to logic 1. reserved bit 6. read as 0, should write to as 0. bs5-bs0 (burst size). this field defines the number of refresh transactions per refresh request made to the z380 mpu's external interface logic. the burst size ranges from 1 to 64, with the highest size specified with bs5-bs0 equal to 0s. refresh wait register t1w2-t1w0 (t1 waits). this binary field defines up to seven t1 wait states to be inserted in refresh transactions. t1w1-t2w0 (t2 waits). this binary field defines up to three t2 wait states to be inserted in refresh transactions. t3w2-t3w0 (t3 waits). this binary field defines up to seven t3 wait states to be inserted in refresh transactions. note that care should be exercised in defining refresh burst size and request intervals to avoid over-burdening the system bus with refresh transactions. the memory chip select signals can be selectively enabled to go active during refresh transactions, such enabling is described in the memory chip selects and waits section. figure 49. refresh register 2 figure 50. refresh waits register rfen 7 -- bs5 bs4 bs3 bs2 bs1 bs0 0 00 0 0 00 0 0 <- reset value rfshr2 : 00000015h r/w burst size reserved refresh enable t1w2 7 t1w1 t1w0 t2w1 t2w0 t3w2 t3w1 t3w0 1 11 1 1 11 1 0 <- reset value rfwr : 0000000fh r/w t3 waits t2 waits t1 waits
m icroprocessor z ilog low power standby mode the z380 mpu provides an optional standby mode to minimize power consumption during system idle time. if this option is enabled, executing the sleep instruction would stop clocking internal to the z380 mpu, as well as at the busclk and ioclk outputs. the /stnby signal goes to active logic 0, indicating the z380 mpu is entering the standby mode. all z380 mpu operations are suspended, the bus control signals are driven inactive and the address bus is driven to logic 1s. note that if an external crystal oscillator is used to drive the z380 mpus clki input, /stnby can be used to stop its operation. this is a means to further reduce power dissipation for the overall system. the standby mode can be exited by asserting any of the /reset, /nmi, /int3-/int0 (if enabled), or optionally, /breq inputs. if the standby mode option is not enabled, the sleep instruction is interpreted and executed no different than the halt instruction, stopping the z30 mpu from further instruction execution. in this case, /halt goes to active logic 0 to indicate the z380 mpu's halt status. standby mode control and entering stby (enable standby mode option). enables the z380 mpu to go into low power standby mode when the sleep instruction is executed. brxt (bus request to exit standby mode). if brxt is at logic 1, standby mode can be exited by asserting /breq. reserved bits 5-3. read as 0s, should write to as 0s. wm2-wm0 (warm-up time selection). wm2-wm0 deter- mines the approximate running duration of a warm-up counter that provides a delay before the z380 mpu resumes its clocking and operations, from the time an interrupt or bus request (if so enabled) is asserted to exit standby mode. in a system where an external crystal oscillator is used to drive the z380 mpus clk input, an appropriate warm-up time can be selected for the oscilla- tor to stabilize. stby 7 brxt wm2 wm1 wm0 0 00 0 0 00 0 0 reset value smcr: 00000016h r/w reserved program as 0s read as 0s bus request to exit standby mode enable standby mode option 00 0 00 1 10 0 01 0 warmup time selection no warmup 2 16 busclk cycles 2 17 busclk cycles 2 19 busclk cycles figure 51. standby mode control register
m icroprocessor z ilog standby mode exit with bus request optionally, if the brxt bit of the standby mode control register (smcr) was previously set, /stnby goes to logic 1 when the /breq input is asserted, allowing the external crystal oscillator that drives the z380 mpus clk input to restart. a warm-up counter internal to the z380 mpu proceeds to count, for a duration long enough for the oscillator to stabilize, which was selected with the wm bits in the smcr. when the counter reaches its end-count, clocking resumes within the z380 mpu and at the busclk and ioclk outputs. the z380 mpu relinquishes the system bus after clocking resumes, with the normal /breq, /back handshake pro- cedure. the z380 mpu regains the system bus when /breq goes inactive, again going through a normal hand- shake procedure. note that clocking continues, and the z380 mpu is at the halt state. busclk ioclk /stnby /back address /breq ffffffffh bus release data bus cntls halt state figure 52. standby mode exit with bus request timing
m icroprocessor z ilog standby mode entering timing figure 53 shows standby mode entering timing in an example where ioclk was programmed to be busclk divided-by-2. note that clocking stops only after ioclk has changed to logic 0. standby mode exit with reset when /reset is asserted, /stnby goes to logic 1, allowing the external crystal oscillator that drives the z380 mpus clki input to restart. the /reset pulse provided should be of a duration long enough for oscillator stabilization. the z380 mpu exits standby mode, and when /reset is deasserted, it goes through the normal reset timing to start instruction execution at address 00000000h. note that clocking resumes within the z380 mpu and at the busclk and ioclk outputs soon after /reset is asserted, when the crystal oscillator is not yet stabilized. busclk ioclk /stnby address data /reset ffffffffh 000000h opcode fetch busclk ioclk /stnby address data bus cntls (/trefr, /trefa, /trefc, /mrd, /mwr, /bhen, /blen, /ioctl3-0) ffffffffh figure 54. standby mode exit with reset timing figure 53. standby mode entering timing
m icroprocessor z ilog standby mode exit with external interrupts standby mode can be exited by asserting input /nmi. asserting the maskable interrupt inputs /int3-/int0 may also exit standby mode, if the global interrupt flag ief1 was previously enabled at logic 1, and for those requests individually enabled, as indicated in the interrupt enable register. when exit conditions are met, /stnby goes to logic 1, allowing the external crystal oscillator that drives the z380 mpus clk input to restart. busclk ioclk /stnby /int3,2,1,0 address /nmi ffffffffh appropriate acknowledge figure 55. standby mode exit with external interrupts timing the z380 mpus internal warm-up counter proceeds to count, for a duration long enough for the oscillator to stabilize, as selected by the wm bits in the standby mode control register. when the counter reaches its end-count, clocking resumes within the z380 mpu, as well as at the busclk and ioclk outputs. the z380 mpu performs an interrupt acknowledge procedure appropriate to the inter- rupt request that initiated the standby mode exit.
m icroprocessor z ilog standby mode for on-chip crystal oscillator the previous discussions have been focused on situations where a direct clock is supplied to the z380 mpu's clki input. such a clock may be sourced by an external crystal with its oscillation circuit. in the case where a crystal is connected to the z380 mpu's on-chip oscillator, all standby functions described earlier apply. items worth noting are as follows. 1. when standby mode is entered, the feedback path for the on-chip oscillator is disabled, reducing power con- sumption. 2. a user can select a warm-up time appropriate for the crystal being used, by programming the wm2-wm0 bits in the standby mode control register (smcr). table 6. z380 mpu on-chip i/o registers register mnemonic on-chip i/o address lower memory chip select register 0 lmcs0 00000000h lower memory chip select register 1 lmcs1 00000001h upper memory chip select register 0 umcs0 00000002h upper memory chip select register 1 umcs1 00000003h midrange memory chip select register 0 mmcs0 00000004h midrange memory chip select register 1 mmcs1 00000005h midrange memory chip select register 2 mmcs2 00000006h midrange memory chip select register 3 mmcs3 00000007h lower memory waits register lmwr 00000008h upper memory waits register umwr 00000009h midrange memory waits register 0 mmwr0 0000000ah midrange memory waits register 1 mmwr1 0000000bh midrange memory waits register 2 mmwr2 0000000ch midrange memory waits register 3 mmwr3 0000000dh i/o waits register iowr 0000000eh refresh waits register rfwr 0000000fh memory selects master enable register msmer 00000010h i/o bus control register 0 iocr0 00000011h i/o bus control register 1 iocr1 00000012h refresh register 0 rfshr 0 00000013h refresh register 1 rfshr1 00000014h refresh register 2 rfshr2 00000015h standby mode control register smcr 00000016h interrupt enable register ier 00000017h assigned vectors base register avbr 00000018h trap and break register trpbk 00000019h
m icroprocessor z ilog reset the z380 mpu is placed in a dormant state when the /reset input is asserted. all its operations are terminated, including any interrupt, bus request or bus transaction that may be in progress. its ioclk goes low on the next busclk rising edge, and enters into the busclk divided- down-by-eight mode. the address and data buses are tri- stated, and the bus control signals are driven to their inactive states. the effect of a reset on the z380 cpu and related i/o registers is depicted in table 6, and the effect on the on-chip peripheral functions is summarized in table 8. the /reset input may be asynchronous to busclk, though it is sampled internally at busclks falling edges. for proper initialization of the z380 mpu, v dd must be within operating specification and its busclk must be stable for more than five cycles with /reset held low. the /reset input has a built-in schmitt trigger buffer to facili- tate power-on reset generation through an rc network. note that if a user system has devices external to the z380 mpu that are clocked by ioclk, these devices may require a /reset pulse width that spans over a number of ioclk cycles (now at busclk/8) for proper initialization. the z380 mpu proceeds to fetch its first instruction 3.5 busclk cycles after /reset is deasserted, provided such deassertion meets the proper setup and hold times with reference to the falling edge of busclk, as depicted in figure 20 in the external interface section. figure 19 in the same section indicates a synchronization of ioclk when /reset is deasserted. again with the proper setup and hold times being met, ioclks first rising edge is 11.5 busclk cycles after the /reset deassertion, preceded by a minimum of 4 busclk cycles where ioclk is at low. note that if /breq is active when /reset is deasserted, the z380 mpu would relinquish the bus instead of fetching its first instruction. ioclk synchronization would still take place as described before.
m icroprocessor z ilog table 7. effect of a reset on z380 cpu and related i/o registers register reset value comments program counter 00000000 pcz, pc stack pointer 00000000 spz, sp i 000000 iz, i r 00 select register 00000000 register bank 0 selected: af, main bank, ix, iy native mode maskable interrupts disabled, in mode 0 bus request lock-off a and f registers register banks 3-0: a, f, a, f unaffected register extensions 0000 register bank 0: bcz, dez, hlz, iyz, bcz, dez, hlz, iyz (all non-extended portions unaffected.) register bank 3-1 unaffected. i/o bus control register 0 00 ioclk = busclk/8 interrupt enable register 01 /int0 enabled assigned vector base register 00 trap and break register 00 table 8. effect of a reset on on-chip peripheral functions peripheral functions reset conditions memory chip selects and waits lower memory chip select signal enabled for lowest 1 mbytes (00000000h-000fffffh), with 7 t1, 3 t2, and 7 t3 waits. upper memory chip select signal enabled for highest 16th mbytes (00f00000h - 00ffffffh), with 7 t1, 3 t2, and 7 t3 waits. midrange memory chip select signal and waits disabled. i/o waits external i/o read, write -- 7 waits. reti -- 3 waits. interrupt daisy chain -- 7 waits. dram refresh controller disabled standby mode disabled
m icroprocessor z ilog absolute maximum ratings voltage on v dd with respect to v ss .......... ?.3v to +7.0v voltage on all pins, with respect to v ss .................... ?.3v to (v dd + 0.3)v operating ambient temperature: .................. 0 to +70? storage temperature: ........................... ?5? to +150? stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the ac and dc characteristics sections below apply for the following standard test conditions, unless otherwise noted. all voltages are referenced to v ss (0v). positive current flows into the referenced pin. standard conditions are as follows: 4.75v < v dd < 5.25v low voltage 3.15 <3.3 <3.45 v ss = 0v standard test load on all outputs. dc characteristics z380 version symbol parameter min max unit note v ih input high voltage 3.0 v dd + 0.3 v v il input low voltage -0.3 0.8 v v oh1 output high voltage (-4 ma i oh ) 2.4 v v oh2 output high voltage (-250 a i oh ) v dd ?0.8 v v v ol output low voltage (4 ma i ol ) 0.5 v i il input leakage current -10 10 a 1 i tl tri-state leakage current -10 10 a 2 i dd1 power supply current (@ 18 mhz) tbs ma 3 i dd3 standby power supply current tbs a 4 c in input capacitance (f =1 mhz) 15 pf 5 c out output capacitance (f =1 mhz) 15 pf 5 c io i/o capacitance (f =1 mhz) 15 pf 5 c l output load capacitance 100 pf c ld ac output derating (above 100 pf) 50 ps/pf notes: 1. 0.4 v < v in < 2.4 v 2. 0.4 v < v out < 2.4 v 3. v dd = 5.0 v, v ih = 4.8 v, v il = 0.2 v 4. v dd = 5.0 v, v ih = 4.8 v, v il = 0.2 v 5. unmeasured pins returned to v ss .
m icroprocessor z ilog ac characteristics z380 version Z8038018 no. symbol parameter min max note 1 tcc clk cycle time 55 2 twch clk width high 24.5 3 twcl clk width low 24.5 4 trc clk rise time 3 5 tfc clk fall time 3 6 tdcf(bcr) clk fall to busclk rise delay 30 7 tdcr(bcf) clk rise to busclk fall delay 27 8 tdbcr(out) busclk rise to output valid delay 6.5 9 tdbcf(out) busclk fall to output valid delay 6.5 10 tsin(bcr) input to busclk rise setup time 16 1 11 thin(bcr) input to busclk rise hold time 0 1 12 tsbr(bcf) /breq to busclk fall setup time 16 2 13 thbr(bcf) /breq to busclk fall hold time 0 2 14 tsmw(bcr) mem wait to busclk rise setup time 16 3 15 thmw(bcr) mem wait to busclk rise hold time 0 3 16 tsmw(bcf) mem wait to busclk fall setup time 24 3 17 thmw(bcf) mem wait to busclk fall hold time 0 3 18 tsiow(bcr) io wait to busclk rise setup time 24 3 19 thiow(bcr) io wait to busclk rise hold time 0 3 20 tsiow(bcf) io wait to busclk fall setup time 24 3 21 thiow(bcf) io wait to busclk fall hold time 0 3 22 twnmi1 /nmi low width 25 23 twres1 reset low width 10 24 tx01(02) output skew (same clock edge) ? +2 4 25 tx01(03) output skew (opposite clock edge) ? +3 5 notes: 1. applicable for data bus and /msize inputs 2. /breq can also be asserted/deasserted asynchronously 3. external waits asserted at /wait input 4. tx01(02) = [output 1] tdbcr(out) - [output 2] tdbcr(out) or [output 1] tdbcf(out) - [output 2] tdbcf(out) 5. tx01(03) = [output 1] tdbcr(out) - [output 3] tdbcf(out) or [output 1] tdbcf(out) - [output 3] tdbcr(out)
m icroprocessor z ilog dc characteristics low voltage z380 version symbol parameter min max unit note v ih input high voltage 2.0 v dd + 0.5 v v il input low voltage ?.5 0.8 v v oh1 output high voltage (?00 a i oh ) 2.15 - v v ol output low voltage (1.6 ma i ol ) - 0.4 v i il input leakage current ?0 10 a 1 i tl tri-state leakage current ?0 10 a 2 i dd1 power supply current (@ 10 mhz) tbs ma 3 i dd3 standby power supply current 20 a 4 c in input capacitance (f =1 mhz) 15 pf 5 c out output capacitance (f =1 mhz) 15 pf 5 c io i/o capacitance (f =1 mhz) 15 pf 5 c l output load capacitance 100 pf c ld ac output derating (above 100 pf) 250 ps/pf notes: 1. v in = 0.4 v 2. 0.4 v < v out < 2.15 v 3. v dd = 3.3 v, v ih = 3.0 v, v il = 0.2 v 4. v dd = 3.3 v, v ih = 3.0 v, v il = 0.2 v 5. unmeasured pins returned to v ss .
m icroprocessor z ilog ac characteristics low voltage z380 z8l38010 no. symbol parameter min max note 1 tcc clk cycle time 100 2 twch clk width high 40 3 twcl clk width low 40 4 trc clk rise time 5 5 tfc clk fall time 5 6 tdcf(bcr) clk fall to busclk rise delay 60 7 tdcr(bcf) clk rise to busclk fall delay 55 8 tdbcr(out) busclk rise to output valid delay 15 9 tdbcf(out) busclk fall to output valid delay 15 10 tsin(bcr) input to busclk rise setup time 30 1 11 thin(bcr) input to busclk rise hold time 0 1 12 tsbr(bcf) /breq to busclk fall setup time 30 2 13 thbr(bcf) /breq to busclk fall hold time 0 2 14 tsmw(bcr) mem wait to busclk rise setup time 30 3 15 thmw(bcr) mem wait to busclk rise hold time 0 3 16 tsmw(bcf) mem wait to busclk fall setup time 45 3 17 thmw(bcf) mem wait to busclk fall hold time 0 3 18 tsiow(bcr) io wait to busclk rise setup time 45 3 19 thiow(bcr) io wait to busclk rise hold time 0 3 20 tsiow(bcf) io wait to busclk fall setup time 45 3 21 thiow(bcf) io wait to busclk fall hold time 0 3 22 twnmi1 /nmi low width 50 23 twres1 reset low width 10 24 tx01(02) output skew (same clock edge) ? +4 4 25 tx01(03) output skew (opposite clock edge) ? +6 5 notes: 1. applicable for data bus and /msize inputs 2. /breq can also be asserted/deasserted asynchronously 3. external waits asserted at /wait input 4. tx01(02) = [output 1] tdbcr(out) - [output 2] tdbcr(out) or [output 1] tdbcf(out) - [output 2] tdbcf(out) 5. tx01(03) = [output 1] tdbcr(out) - [output 3] tdbcf(out) or [output 1] tdbcf(out) - [output 3] tdbcr(out)
m icroprocessor z ilog clk busclk output output input /nmi 1 3 2 4 6 7 8 9 input 10 5 22 14 18 11 15 19 12 16 20 13 17 21 /reset 23 ac characteristics (continued) figure 56. z380 cpu timing
m icroprocessor z ilog appendix a no esc ed esc dd esc fd esc cb esc ed-cb dd-cb fd-cb 00 nop in0 b,(n) - - rlc b rlcw bc - - 01 ld bc,nn out0 (n),b ld (bc),ix ld (bc),iy rlc c rlcw de ldbc,(sp+d) - 02 ld (bc),a ld bc,bc ld bc,de ld bc,hl rlc d rlcw (hl) rlcw (ix+d) rlcw (iy+d) 03 inc bc ** ex bc,ix ld ix,(bc) ld iy,(bc) rlc e rlcw hl ld bc,(ix+d) ldbc,(iy+d) 04 inc b tst b - - rlc h rlcw ix - - 05 dec b ex bc,de - - rlc l rlcw iy - - 06 ld b,n ld (bc),nn - - rlc (hl) - rlc (ix+d) rlc (iy+d) 07 rlca ex a,b ld ix,bc ld iy,bc rlc a - - - 08 ex af,af in0 c,(n) - - rrc b rrcw bc - - 09 add hl,bc ** out0 (n),c add ix,bc ** add iy,bc ** rrc c rrcw de ld (sp+d),bc - 0a ld a,(bc) - - - rrc d rrcw (hl) rrcw (ix+d) rrcw (iy+d) 0b dec bc ** ex bc,iy ld bc,ix ld bc,iy rrc e rrcw hl ld (ix+d),bc ld (iy+d),bc 0c inc c tst c ld bc,(bc) ld (bc),bc rrc h rrcw ix - - 0d dec c ex bc,hl ld bc,(de) ld (de),bc rrc l rrcw iy - - 0e ld c,n swap bc - - rrc (hl) - rrc (ix+d) rrc (iy+d) 0f rrca ex a,c ld bc,(hl) ld (hl),bc rrc a - - - 10 djnz e in0 d,(n) djnz ee djnz eee rl b rlw bc - - 11 ld de,nn out0 (n),d ld (de),ix ld (de),iy rl c rlw de ld de,(sp+d) - 12 ld (de),a ld de,bc ld de,de ld de,hl rl d rlw (hl) rlw (ix+d) rlw (iy+d) 13 inc de ** ex de,ix ld ix,(de) ld iy,(de) rl e rlw hl ld de,(ix+d) ld de,(iy+d) 14 inc d tst d - - rl h rlw ix - - 15 dec d - - - rl l rlw iy - - 16 ld d,n ld (de),nn - - rl (hl) - rl (ix+d) rl (iy+d) 17 rla ex a,d ld ix,de ld iy,de rl a - - - 18 jr e in0 e,(n) jr ee jr eee rr b rrw bc - - 19 add hl,de ** out0 (n),e add ix,de ** add iy,de ** rr c rrw de ld (sp+d),de - 1a ld a,(de) - - - rr d rrw (hl) rrw (ix+d) rrw (iy+d) 1b dec de ** ex de,iy ld de,ix ld de,iy rr e rrw hl ld (ix+d),de ld (iy+d),de 1c inc e tst e ld de,(bc) ld (bc),de rr h rrw ix - - 1d dec e - ld de,(de) ld (de),de rr l rrw iy - - 1e ld e,n swap de - - rr (hl) - rr (ix+d) rr (iy+d) 1f rra ex a,e ld de,(hl) ld (hl),de rr a - - - 20 jr nz,e in0 h,(n) jr nz,ee jr nz,eee sla b slaw bc - - 21 ld hl,nn out0 (n),h ld ix,nn ld iy,nn sla c slaw de ld ix,(sp+d) ld iy,(sp+d) 22 ld (nn),hl - ld (nn),ix ld (nn),iy sla d slaw (hl) slaw (ix+d) slaw (iy+d) 23 inc hl ** - inc ix ** inc iy ** sla e slaw hl ld iy,(ix+d) ld ix,(iy+d) 24 inc h tst h inc ixu inc iyu sla h slaw ix - - 25 dec h - dec ixu dec iyu sla l slaw iy - - 26 ld h,n - ld ixu,n ld iyu,n sla (hl) - sla (ix+d) sla (iy+d) 27 daa ex a,h ld ix,iy ld iy,ix sla a - - - 28 jr z,e in0 l,(n) jr z,ee jr z,eee sra b sraw bc - - 29 add hl,hl ** out0 (n),l add ix,ix ** add iy,iy ** sra c sraw de ld (sp+d),ix ld (sp+d),iy 2a ld hl,(nn) - ld ix,(nn) ld iy,(nn) sra d sraw (hl) sraw (ix+d) sraw (iy+d) 2b dec hl ** ex ix,iy dec ix ** dec iy ** sra e sraw hl ld (ix+d),iy ld (iy+d),ix 2c inc l tst l inc ixl inc iyl sra h sraw ix - - 2d dec l - dec ixl dec iyl sra l sraw iy - - 2e ld l,n - ld ixl,n ld iyl,n sra (hl) - sra (ix+d) sra (iy+d) 2f cpl ex a,l cplw - sra a - - - 30 jr nc,e in0 (n) jr nc,ee jr nc,eee ex b,b ex bc,bc - -
m icroprocessor z ilog appendix a (continued) no esc ed esc dd esc fd esc cb esc ed-cb dd-cb fd-cb 31 ld sp,nn - ld (hl),ix ld (hl),iy ex c,c ex de,de ld hl,(sp+d) - 32 ld (nn),a ld hl,bc ld hl,de ld hl,hl ex d,d - - - 33 inc sp ** ex hl,ix ld ix,(hl) ld iy,(hl) ex e,e ex hl,hl ld hl,(ix+d) ld hl,(iy+d) 34 inc (hl) tst (hl) inc (ix+d) inc (iy+d) ex h,h ex ix,ix- - 35 dec (hl) - dec (ix+d) dec (iy+d) ex l,l ex iy,iy - - 36 ld (hl),n ld (hl),nn ld (ix+d),n ld (iy+d),n - - - 37 scf ex a,(hl) ld ix,hl ld iy,hl ex a,a - - - 38 jr c,e in0 a,(n) jr c,ee jr c,eee srl b srlw bc - - 39 add hl,sp ** out0 (n),a add ix,sp ** add iy,sp ** srl c srlw de ld (sp+d),hl- 3a ld a,(nn) - - - srl d srlw (hl) slrw (ix+d) srlw (iy+d) 3b dec sp ** ex hl,iy ld hl,ix ld hl,iy srl e srlw hl ld (ix+d),hl ld (iy+d),hl 3c inc a tst a ld hl,(bc) ld (bc),hl srl h srlw ix - - 3d dec a - ld hl,(de) ld (de),hl srl l srlw iy - - 3e ld a,n swap hl swap ix swap iy srl (hl) - srl (ix+d) srl (iy+d) 3f ccf ex a,a ld hl,(hl) ld (hl),hl srl a - - - 40 ld b,b in b,(c) inw bc,(c) - bit 0,b - - - 41 ld b,c out (c),b outw (c),bc - bit 0,c - - - 42 ld b,d sbc hl,bc - - bit 0,d - - - 43 ld b,e ld (nn),bc - - bit 0,e - - - 44 ld b,h neg ld b,ixu ld b,iyu bit 0,h - - - 45 ld b,l retn ld b,ixl ld b,iyl bit 0,l - - - 46 ld b,(hl) im 0 ld b,(ix+d) ld b,(iy+d) bit 0,(hl) - bit 0,(ix+d) bit 0,(iy+d) 47 ld b,a ld i,a ld i,hl - bit 0,a - - - 48 ld c,b in c,(c) - - bit 1,b - - - 49 ld c,c out (c),c - - bit 1,c - - - 4a ld c,d adc hl,bc - - bit 1,d - - - 4b ld c,e ld bc,(nn) - - bit 1,e - - - 4c ld c,h mlt bc ld c,ixu ld c,iyu bit 1,h - - - 4d ld c,l reti ld c,ixl ld c,iyl bit 1,l - - - 4e ld c,(hl) im 3 ld c,(ix+d) ld c,(iy+d) bit 1,(hl) - bit 1,(ix+d) bit 1,(iy+d) 4f ld c,a ld r,a - - bit 1,a - - - 50 ld d,b in d,(c) inw de,(c) - bit 2,b - - - 51 ld d,c out (c),d outw (c),de - bit 2,c - - - 52 ld d,d sbc hl,de - - bit 2,d - - - 53 ld d,e ld (nn),de - - bit 2,e - - - 54 ld d,h negw ld d,ixu ld d,iyu bit 2,h - - - 55 ld d,l retb ld d,ixl ld d,iyl bit 2,l - - - 56 ld d,(hl) im 1 ld d,(ix+d) ld d,(iy+d) bit 2,(hl) - bit 2,(ix+d) bit 2,(iy+d) 57 ld d,a ld a,i ld hl,i - bit 2,a - - - 58 ld e,b in e,(c) - - bit 3,b - - - 59 ld e,c out (c),e - - bit 3,c - - - 5a ld e,d adc hl,de - - bit 3,d - - - 5b ld e,e ld de,(nn) - - bit 3,e - - - 5c ld e,h mlt de ld e,ixu ld e,iyu bit 3,h - - - 5d ld e,l - ld e,ixl ld e,iyl bit 3,l - - - 5e ld e,(hl) im 2 ld e,(ix+d) ld e,(iy+d) bit 3,(hl) - bit 3,(ix+d) bit 3,(iy+d) 5f ld e,a ld a,r - - bit 3,a - - - 60 ld h,b in h,(c) ld ixu,b ld iyu,b bit 4,b - - - 61 ld h,c out (c),h ld ixu,c ld iyu,c bit 4,c - - - 62 ld h,d sbc hl,hl ld ixu,d ld iyu,d bit 4,d - - - 63 ld h,e ld (nn),hl ld ixu,e ld iyu,e bit 4,e - - - 64 ld h,h tst m ld ixu,ixu ld iyu,iyu bit 4,h - - - 65 ld h,l exts ld ixu,ixl ld iyu,iyl bit 4,l - - -
m icroprocessor z ilog no esc ed esc dd esc fd esc cb esc ed-cb dd-cb fd-cb 66 ld h,(hl) - ld h,(ix+d) ld h,(iy+d) bit 4,(hl) - bit 4,(ix+d) bit 4,(iy+d) 67 ld h,a rrd ld ixu,a ld iyu,a bit 4,a - - - 68 ld l,b in l,(c) ld ixl,b ld iyl,b bit 5,b - - - 69 ld l,c out (c),l ld ixl,c ld iyl,c bit 5,c - - - 6a ld l,d adc hl,hl ld ixl,d ld iyl,d bit 5,d - - - 6b ld l,e ld hl,(nn) ld ixl,e ld iyl,e bit 5,e - - - 6c ld l,h mlt hl ld ixl,ixu ld iyl,iyu bit 5,h - - - 6d ld l,l - ld ixl,ixl ld iyl,iyl bit 5,l - - - 6e ld l,(hl) - ld l,(ix+d) ld l,(iy+d) bit 5,(hl) - bit 5,(ix+d) bit5,(iy+d) 6f ld l,a rld ld ixl,a ld iyl,a bit 5,a - - - 70 ld (hl),b - ld (ix+d),b ld (iy+d),b bit 6,b - - - 71 ld (hl),c out (c),n ld (ix+d),c ld (iy+d),c bit 6,c - - - 72 ld (hl),d sbc hl,sp ld (ix+d),d ld (iy+d),d bit 6,d - - - 73 ld (hl),e ld (nn),sp ld (ix+d),e ld (iy+d),e bit 6,e - - - 74 ld (hl),h tstio m ld (ix+d),h ld (iy+d),h bit 6,h - - - 75 ld (hl),l extsw ld (ix+d),l ld (iy+d),l bit 6,l - - - 76 halt slp - - bit 6,(hl) - bit 6,(ix+d) bit 6,(iy+d) 77 ld (hl),a - ld (ix+d),a ld (iy+d),a bit 6,a - - - 78 ld a,b in a,(c) inw hl,(c) - bit 7,b - - - 79 ld a,c out (c),a outw (c),hl outw (c),nn bit 7,c - - - 7a ld a,d adc hl,sp - - bit 7,d - - - 7b ld a,e ld sp,(nn) - - bit 7,e - - - 7c ld a,h mlt sp ld a,ixu ld a,iyu bit 7,h - - - 7d ld a,l - ld a,ixl ld a,iyl bit 7,l - - - 7e ld a,(hl) - ld a,(ix+d) ld a,(iy+d) bit 7,(hl) - bit 7,(ix+d) bit 7,(iy+d) 7f ld a,a - - - bit 7,a - - - 80 add a,b - - - res 0,b - - - 81 add a,c - - - res 0,c - - - 82 add a,d add sp,nn ** - - res 0,d - - - 83 add a,e otim - - res 0,e - - - 84 add a,h addw bc add ixu add iyu res 0,h - - - 85 add a,l addw de add ixl add iyl res 0,l - - - 86 add a,(hl) addw nn add a,(ix+d) add a,(iy+d) res 0,(hl) - res 0,(ix+d) res 0,(iy+d) 87 add a,a addw hl addw ix addw iy res 0,a - - - 88 adc a,b - - - res 1,b - - - 89 adc a,c - - - res 1,c - - - 8a adc a,d - - - res 1,d - - - 8b adc a,e otdm - - res 1,e - - - 8c adc a,h adcw bc adc a,ixu adc a,iyu res 1,h - - - 8d adc a,l adcw de adc a,ixl adc a,iyl res 1,l - - - 8e adc a,(hl) adcw nn adc a,(ix+d) adc a,(iy+d) res 1,(hl) - res 1,(ix+d) res 1,(iy+d) 8f adc a,a adcw hl adcw ix adcw iy res 1,a - - - 90 sub b - - - res 2,b multw bc - - 91 sub c - - - res 2,c multw de - - 92 sub d sub sp,nn ** - - res 2,d - multw (ix+d) multw (iy+d) 93 sub e otimr - - res 2,e multw hl - - 94 sub h subw bc sub ixu sub iyu res 2,h multw ix - - 95 sub l subw de sub ixl sub iyl res 2,l multw iy - - 96 sub (hl) subw nn sub (ix+d) sub (iy+d) res 2,(hl) - res 2,(ix+d) res 2,(iy+d) 97 sub a subw hl subw ix subw iy res 2,a multw nn - -
m icroprocessor z ilog appendix a (continued) no esc ed esc dd esc fd esc cb esc ed-cb dd-cb fd-cb 98 sbc a,b - - - res 3,b multuw bc - - 99 sbc a,c - - - res 3,c multuw de - - 9a sbc a,d - - - res 3,d - multuw (ix+d) multuw (iy+d) 9b sbc a,e otdmr - - res 3,e multuw hl - - 9c sbc a,h sbcw bc sbc a,ixu sbc a,iyu res 3,h multuw ix - - 9d sbc a,l sbcw de sbc a,ixl sbc a,iyl res 3,l multuw iy - - 9e sbc a,(hl) sbcw nn sbc a,(ix+d) sbc a,(iy+d) res 3,(hl) - res 3,(ix+d) res 3,(iy+d) 9f sbc a,a sbcw hl sbcw ix sbcw iy res 3,a multuw nn - - a0 and b ldi - - res 4,b - - - a1 and c cpi - - res 4,c - - - a2 and d ini - - res 4,d - - - a3 and e outi - - res 4,e - - - a4 and h andw bc and ixu and iyu res 4,h - - - a5 and l andw de and ixl and iyl res 4,l - - - a6 and (hl) andw nn and (ix+d) and (iy+d) res 4,(hl) - res 4,(ix+d) res 4,(iy+d) a7 and a andw hl andw ix andw iy res 4,a - - - a8 xor b ldd - - res 5,b - - - a9 xor c cpd - - res 5,c - - - aa xor d ind - - res 5,d - - - ab xor e outd - - res 5,e - - - ac xor h xorw bc xor ixu xor iyu res 5,h - - - ad xor l xorw de xor ixl xor iyl res 5,l - - - ae xor (hl) xorw nn xor (ix+d) xor (iy+d) res 5,(hl) - res 5,(ix+d) res 5,(iy+d) af xor a xorw hl xorw ix xorw iy res 5,a - - - b0 or b ldir - - res a,b - - - b1 or c cpir - - res 6,c - - - b2 or d inir - - res 6,d - - - b3 or e otir - - res 6,e - - - b4 or h orw bc or ixu or iyu res 6,h - - - b5 or l orw de or ixl or iyl res 6,l - - - b6 or (hl) orw nn or (ix+d) or (iy+d) res 6,(hl) - res 6,(ix+d) res 6,(iy+d) b7 or a orw hl orw ix orw iy res 6,a - - - b8 cp b lddr - - res 7,b divuw bc - - b9 cp c cpdr - - res 7,c divuw de - - ba cp d indr - - res 7,d - divuw (ix+d) divuw (iy+d) bb cp e otdr - - res 7,e divuw hl - - bc cp h cpw bc cp ixu cp iyu res 7,h divuw ix - - bd cp l cpw de cp ixl cp iyl res 7,l divuw iy - - be cp (hl) cpw nn cp (ix+d) cp (iy+d) res 7,(hl) - res 7,(ix+d) res 7,(iy+d) bf cp a cpw hl cpw ix cpw iy res 7,a divuw nn - - c0 ret nz ldctl hl,sr ddir w ddir lw set 0,b - - - c1 pop bc pop sr ddir ib,w ddir ib,lw set 0,c - - - c2 jp nz,nn - ddir iw,w ddir iw,lw set 0,d - - - c3 jp nn - ddir ib ddir iw set 0,e - - - c4 call nz,nn calr nz,e calr nz,ee calr nz,eee set 0,h - - - c5 push bc push sr - - set 0,l - - - c6 add a,n add hl,(nn) ** addw (ix+d) addw (iy+d) set 0,(hl) - set 0,(ix+d) set 0,(iy+d) c7 rst 0 - - - set 0,a - - - c8 ret z ldctl sr,hl ldctl sr,a - set 1,b - - - c9 ret - - - set 1,c - - -
m icroprocessor z ilog no esc ed esc dd esc fd esc cb esc ed-cb dd-cb fd-cb ca jp z,nn - ldctl sr,n - set 1,d - - - cb escape escape escape escape set 1,e - - - cc call z,nn calr z,e calr z,ee calr z,eee set 1,h - - - cd call nn calr e calr ee calr eee set 1,l - - - ce adc a,n - adcw (ix+d) adcw (iy+d) set 1,(hl) - set 1,(ix+d) set 1,(iy+d) cf rst 1 btest mtest - set 1,a - - - d0 ret nc ldctl a,dsr ldctl a,xsr ldctl a,ysr set 2,b - - - d1 pop de - - - set 2,c - - - d2 jp nc,nn - - - set 2,d - - - d3 out (n),a outa (nn),a - outaw (nn),hl set 2,e - - - d4 call nc,nn calr nc,e calr nc,ee calr nc,eee set 2,h - - - d5 push de - - - set 2,l - - - d6 sub n sub hl,(nn) ** subw (ix+d) subw (iy+d) set 2,(hl) - set 2,(ix+d) set 2,(iy+d) d7 rst 2 - - - set 2,a - - - d8 ret c ldctl dsr,a ldctl xsr,a ldctl ysr,a set 3,b - - - d9 exx exall exxx exxy set 3,c - - - da jp c,nn ldctl dsr,n ldctl xsr,n ldctl ysr,n set 3,d - - - db in a,(n) ina a,(nn) - inaw hl,(nn) set 3,e - - - dc call c,nn calr c,e calr c,ee calr c,eee set 3,h - - - dd escape reserved reserved reserved set 3,l - - - de sbc a,n - sbcw (ix+d) sbcw (iy+d) set 3,(hl) - set 3,(ix+d) set 3,(iy+d) df rst 3 - - - set 3,a - - - e0 ret po ldiw - - set 4,b - - - e1 pop hl - pop ix pop iy set 4,c - - - e2 jp po,nn iniw - - set 4,d - - - e3 ex (sp),hl outiw ex (sp),ix ex (sp),iy set 4,e - - - e4 call po,nn calr po,e calr po,ee calr po,eee set 4,h - - - e5 push hl - push ix push iy set 4,l - - - e6 and n - andw (ix+d) andw (iy+d) set 4,(hl) - set 4,(ix+d) set 4,(iy+d) e7 rst 4 - - - set 4,a - - - e8 ret pe lddw - - set 5,b - - - e9 jp (hl) - jp (ix) jp (iy) set 5,c - - - ea jp pe,nn indw - - set 5,d - - - eb ex de,hl outdw - - set 5,e - - - ec call pe,nn calr pe,e calr pe,ee calr pe,eee set 5,h - - - ed escape reserved reserved reserved set 5,l - - - ee xor n - xorw (ix+d) xorw (iy+d) set 5,(hl) - set 5,(ix+d) set 5,(iy+d) ef rst 5 - - - set 5,a - - - f0 ret p ldirw - - set 6,b - - - f1 pop af - - - set 6,c - - - f2 jp p,nn inirw - - set 6,d - - - f3 di otirw di n - set 6,e - - - f4 call p,nn calr p,e calr p,ee calr p,eee set 6,h - - - f5 push af - - push nn set 6,l - - - f6 or n - orw (ix+d) orw (iy+d) set 6,(hl) - set 6,(ix+d) set 6,(iy+d) f7 rst 6 setc lck setc lw setc xm set 6,a - - - f8 ret m lddrw - - set 7,b - - - f9 ld sp,hl - ld sp,ix ld sp,iy set 7,c - - - fa jp m,nn indrw - - set 7,d - - - fb ei otdrw ei n - set 7,e - - - fc call m,nn calr m,e calr m,ee calr m,eee set 7,h - - - fd escape reserved reserved reserved set 7,l - - - fe cp n - cpw (ix+d) cpw (iy+d) set 7,(hl) - set 7,(ix+d) set 7,(iy+d) ff rst 7 resc lck resc lw - set 7,a - - -
m icroprocessor z ilog package information 100-lead qfp package diagram
m icroprocessor z ilog ordering information z380 mpu 18 mhz 10 mhz, 3 volts 100-pin qfp 100-pin qfp Z8038018fsc z8l38010fsc package f = plastic quad flat pack temperature s = 0? to +70? environmental c = plastic standard flow example: z 80380 18 f s c environmental flow temperature package speed product number zilog prefix is a z380, 18 mhz, plastic quad flat pack, 0? to +70?, plastic standard flow zilogs products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 telex 910-338-7621 fax 408 370-8056 internet: http://www.zilog.com 1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the informa- tion set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of mer- chantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document.

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